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/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/
Dfloat_args.ll3 …bal-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
7 ; FP32-LABEL: name: float_in_fpr
8 ; FP32: bb.1.entry:
9 ; FP32: liveins: $f12, $f14
10 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
11 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
12 ; FP32: $f0 = COPY [[COPY1]](s32)
13 ; FP32: RetRA implicit $f0
26 ; FP32-LABEL: name: double_in_fpr
27 ; FP32: bb.1.entry:
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
Dfptosi_and_fptoui.mir2 …sel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
32 ; FP32-LABEL: name: f32toi64
33 ; FP32: liveins: $f12
34 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
35 ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
36 ; FP32: $f12 = COPY [[COPY]](s32)
37 …; FP32: JAL &__fixsfdi, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $…
38 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
39 ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
40 ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
[all …]
Dsitofp_and_uitofp.mir2 …sel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
32 ; FP32-LABEL: name: i64tof32
33 ; FP32: liveins: $a0, $a1
34 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
35 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
36 ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
37 ; FP32: $a0 = COPY [[COPY]](s32)
38 ; FP32: $a1 = COPY [[COPY1]](s32)
39 …; FP32: JAL &__floatdisf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1,…
40 ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY $f0
[all …]
Dfloat_arithmetic_operations.mir2 …sel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
25 ; FP32-LABEL: name: float_add
26 ; FP32: liveins: $f12, $f14
27 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
28 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
29 ; FP32: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]
30 ; FP32: $f0 = COPY [[FADD]](s32)
31 ; FP32: RetRA implicit $f0
54 ; FP32-LABEL: name: float_sub
55 ; FP32: liveins: $f12, $f14
[all …]
Dceil_and_floor.mir2 …sel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
20 ; FP32-LABEL: name: ceil_f32
21 ; FP32: liveins: $f12
22 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
23 ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
24 ; FP32: $f12 = COPY [[COPY]](s32)
25 ; FP32: JAL &ceilf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $f0
26 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f0
27 ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
28 ; FP32: $f0 = COPY [[COPY1]](s32)
[all …]
Dfcmp.mir2 …sel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
18 ; FP32-LABEL: name: oeq_s
19 ; FP32: liveins: $f12, $f14
20 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
21 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
22 ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]]
23 ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
24 ; FP32: $v0 = COPY [[COPY2]](s32)
25 ; FP32: RetRA implicit $v0
50 ; FP32-LABEL: name: oeq_d
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
Dfcmp.mir2 …-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
51 ; FP32-LABEL: name: false_s
52 ; FP32: liveins: $f12, $f14
53 ; FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0
54 ; FP32: $v0 = COPY [[ORi]]
55 ; FP32: RetRA implicit $v0
77 ; FP32-LABEL: name: true_s
78 ; FP32: liveins: $f12, $f14
79 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
80 ; FP32: $v0 = COPY [[ADDiu]]
[all …]
Dfloat_arithmetic_operations.mir2 …-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
26 ; FP32-LABEL: name: float_add
27 ; FP32: liveins: $f12, $f14
28 ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
29 ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
30 ; FP32: [[FADD_S:%[0-9]+]]:fgr32 = FADD_S [[COPY]], [[COPY1]]
31 ; FP32: $f0 = COPY [[FADD_S]]
32 ; FP32: RetRA implicit $f0
57 ; FP32-LABEL: name: float_sub
58 ; FP32: liveins: $f12, $f14
[all …]
Dfloat_args.mir2 …-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
26 ; FP32-LABEL: name: float_in_fpr
27 ; FP32: liveins: $f12, $f14
28 ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f14
29 ; FP32: $f0 = COPY [[COPY]]
30 ; FP32: RetRA implicit $f0
51 ; FP32-LABEL: name: double_in_fpr
52 ; FP32: liveins: $d6, $d7
53 ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d7
54 ; FP32: $d0 = COPY [[COPY]]
[all …]
Dsitofp_and_uitofp.mir2 …-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
21 ; FP32-LABEL: name: i32tof32
22 ; FP32: liveins: $a0
23 ; FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
24 ; FP32: [[PseudoCVT_S_W:%[0-9]+]]:fgr32 = PseudoCVT_S_W [[COPY]]
25 ; FP32: $f0 = COPY [[PseudoCVT_S_W]]
26 ; FP32: RetRA implicit $f0
49 ; FP32-LABEL: name: i32tof64
50 ; FP32: liveins: $a0
51 ; FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
[all …]
Dfloat_constants.mir2 …-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
18 ; FP32-LABEL: name: e_single_precision
19 ; FP32: [[LUi:%[0-9]+]]:gpr32 = LUi 16429
20 ; FP32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 63572
21 ; FP32: [[MTC1_:%[0-9]+]]:fgr32 = MTC1 [[ORi]]
22 ; FP32: $f0 = COPY [[MTC1_]]
23 ; FP32: RetRA implicit $f0
43 ; FP32-LABEL: name: e_double_precision
44 ; FP32: [[LUi:%[0-9]+]]:gpr32 = LUi 16389
45 ; FP32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 48906
[all …]
Dfptosi_and_fptoui.mir2 …-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
20 ; FP32-LABEL: name: f32toi32
21 ; FP32: liveins: $f12
22 ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
23 ; FP32: [[TRUNC_W_S:%[0-9]+]]:fgr32 = TRUNC_W_S [[COPY]]
24 ; FP32: [[MFC1_:%[0-9]+]]:gpr32 = MFC1 [[TRUNC_W_S]]
25 ; FP32: $v0 = COPY [[MFC1_]]
26 ; FP32: RetRA implicit $v0
50 ; FP32-LABEL: name: f64toi32
51 ; FP32: liveins: $d6
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/
Dsitofp_and_uitofp.ll2 …psel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32
141 ; FP32-LABEL: u32tof32:
142 ; FP32: # %bb.0: # %entry
143 ; FP32-NEXT: lui $1, 17200
144 ; FP32-NEXT: mtc1 $4, $f0
145 ; FP32-NEXT: mtc1 $1, $f1
146 ; FP32-NEXT: lui $2, 17200
147 ; FP32-NEXT: ori $1, $zero, 0
148 ; FP32-NEXT: mtc1 $1, $f2
149 ; FP32-NEXT: mtc1 $2, $f3
[all …]
Dfptosi_and_fptoui.ll2 …psel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32
232 ; FP32-LABEL: f64tou32:
233 ; FP32: # %bb.0: # %entry
234 ; FP32-NEXT: trunc.w.d $f0, $f12
235 ; FP32-NEXT: mfc1 $1, $f0
236 ; FP32-NEXT: lui $3, 16864
237 ; FP32-NEXT: ori $2, $zero, 0
238 ; FP32-NEXT: mtc1 $2, $f0
239 ; FP32-NEXT: mtc1 $3, $f1
240 ; FP32-NEXT: sub.d $f2, $f12, $f0
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
Dfloat_arithmetic_operations.mir2 …linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
26 ; FP32-LABEL: name: float_add
27 ; FP32: liveins: $f12, $f14
28 ; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
29 ; FP32: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
30 ; FP32: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[COPY]], [[COPY1]]
31 ; FP32: $f0 = COPY [[FADD]](s32)
32 ; FP32: RetRA implicit $f0
56 ; FP32-LABEL: name: float_sub
57 ; FP32: liveins: $f12, $f14
[all …]
Dfloat_args.mir2 …linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
26 ; FP32-LABEL: name: float_in_fpr
27 ; FP32: liveins: $f12, $f14
28 ; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f14
29 ; FP32: $f0 = COPY [[COPY]](s32)
30 ; FP32: RetRA implicit $f0
50 ; FP32-LABEL: name: double_in_fpr
51 ; FP32: liveins: $d6, $d7
52 ; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d7
53 ; FP32: $d0 = COPY [[COPY]](s64)
[all …]
Dsitofp_and_uitofp.mir2 …linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
20 ; FP32-LABEL: name: i32tof32
21 ; FP32: liveins: $a0
22 ; FP32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
23 ; FP32: [[SITOFP:%[0-9]+]]:fprb(s32) = G_SITOFP [[COPY]](s32)
24 ; FP32: $f0 = COPY [[SITOFP]](s32)
25 ; FP32: RetRA implicit $f0
47 ; FP32-LABEL: name: i32tof64
48 ; FP32: liveins: $a0
49 ; FP32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
[all …]
Dfcmp.mir2 …linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
19 ; FP32-LABEL: name: oeq_s
20 ; FP32: liveins: $f12, $f14
21 ; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
22 ; FP32: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
23 ; FP32: [[FCMP:%[0-9]+]]:gprb(s32) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]]
24 ; FP32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[FCMP]](s32)
25 ; FP32: $v0 = COPY [[COPY2]](s32)
26 ; FP32: RetRA implicit $v0
52 ; FP32-LABEL: name: oeq_d
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZInstrHFP.td22 def LTER : UnaryRR <"lter", 0x32, null_frag, FP32, FP32>;
32 def LEDR : UnaryRR <"ledr", 0x35, null_frag, FP32, FP64>;
33 def LEXR : UnaryRRE<"lexr", 0xB366, null_frag, FP32, FP128>;
36 def LRER : UnaryRR <"lrer", 0x35, null_frag, FP32, FP64>;
41 def LDER : UnaryRRE<"lder", 0xB324, null_frag, FP64, FP32>;
42 def LXER : UnaryRRE<"lxer", 0xB326, null_frag, FP128, FP32>;
50 def CEFR : UnaryRRE<"cefr", 0xB3B4, null_frag, FP32, GR32>;
54 def CEGR : UnaryRRE<"cegr", 0xB3C4, null_frag, FP32, GR64>;
61 def CFER : BinaryRRFe<"cfer", 0xB3B8, GR32, FP32>;
65 def CGER : BinaryRRFe<"cger", 0xB3C8, GR64, FP32>;
[all …]
DSystemZInstrFP.td21 def SelectF32 : SelectWrapper<f32, FP32>;
28 defm CondStoreF32 : CondStores<FP32, simple_store,
39 def LZER : InherentRRE<"lzer", 0xB374, FP32, fpimm0>;
45 def LER : UnaryRR <"ler", 0x38, null_frag, FP32, FP32>;
51 def LDR32 : UnaryRR<"ldr", 0x28, null_frag, FP32, FP32>;
57 defm LTEBR : LoadAndTestRRE<"ltebr", 0xB302, FP32>;
65 defm : CompareZeroFP<LTEBRCompare, FP32>;
74 def LTEBRCompare_VecPseudo : Pseudo<(outs), (ins FP32:$R1, FP32:$R2), []>;
79 defm : CompareZeroFP<LTEBRCompare_VecPseudo, FP32>;
89 // fcopysign with an FP32 result.
[all …]
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZInstrHFP.td22 def LTER : UnaryRR <"lter", 0x32, null_frag, FP32, FP32>;
32 def LEDR : UnaryRR <"ledr", 0x35, null_frag, FP32, FP64>;
33 def LEXR : UnaryRRE<"lexr", 0xB366, null_frag, FP32, FP128>;
36 def LRER : UnaryRR <"lrer", 0x35, null_frag, FP32, FP64>;
41 def LDER : UnaryRRE<"lder", 0xB324, null_frag, FP64, FP32>;
42 def LXER : UnaryRRE<"lxer", 0xB326, null_frag, FP128, FP32>;
50 def CEFR : UnaryRRE<"cefr", 0xB3B4, null_frag, FP32, GR32>;
54 def CEGR : UnaryRRE<"cegr", 0xB3C4, null_frag, FP32, GR64>;
61 def CFER : BinaryRRFe<"cfer", 0xB3B8, GR32, FP32>;
65 def CGER : BinaryRRFe<"cger", 0xB3C8, GR64, FP32>;
[all …]
DSystemZInstrFP.td21 def SelectF32 : SelectWrapper<f32, FP32>;
28 defm CondStoreF32 : CondStores<FP32, simple_store,
39 def LZER : InherentRRE<"lzer", 0xB374, FP32, fpimm0>;
45 def LER : UnaryRR <"ler", 0x38, null_frag, FP32, FP32>;
51 def LDR32 : UnaryRR<"ldr", 0x28, null_frag, FP32, FP32>;
57 defm LTEBR : LoadAndTestRRE<"ltebr", 0xB302, FP32>;
65 defm : CompareZeroFP<LTEBRCompare, FP32>;
74 def LTEBRCompare_VecPseudo : Pseudo<(outs), (ins FP32:$R1, FP32:$R2), []>;
79 defm : CompareZeroFP<LTEBRCompare_VecPseudo, FP32>;
89 // fcopysign with an FP32 result.
[all …]
/external/llvm/lib/Target/SystemZ/
DSystemZInstrFP.td15 def SelectF32 : SelectWrapper<FP32>;
19 defm CondStoreF32 : CondStores<FP32, nonvolatile_store,
30 def LZER : InherentRRE<"lzer", 0xB374, FP32, (fpimm0)>;
37 def LER : UnaryRR <"le", 0x38, null_frag, FP32, FP32>;
43 def LDR32 : UnaryRR<"ld", 0x28, null_frag, FP32, FP32>;
49 defm LTEBR : LoadAndTestRRE<"lteb", 0xB302, FP32>;
57 defm : CompareZeroFP<LTEBRCompare, FP32>;
65 def LTEBRCompare_VecPseudo : Pseudo<(outs), (ins FP32:$R1, FP32:$R2), []>;
70 defm : CompareZeroFP<LTEBRCompare_VecPseudo, FP32>;
79 // fcopysign with an FP32 result.
[all …]
/external/llvm-project/llvm/test/MC/ARM/
Dmve-fp-registers.s45 # FP32: vldmia r0, {d0} @ encoding: [0x90,0xec,0x02,0x0b]
49 # FP32: vpop {{.*}} @ encoding: [0xbd,0xec,0x20,0x0b]
53 # FP32: vpop {{.*}} @ encoding: [0xbd,0xec,0x20,0x0b]
57 # FP32: vstmia r0, {d0} @ encoding: [0x80,0xec,0x02,0x0b]
61 # FP32: vpush {{.*}} @ encoding: [0x2d,0xed,0x20,0x0b]
65 # FP32: vpush {{.*}} @ encoding: [0x2d,0xed,0x20,0x0b]
69 # FP32: vldmia r0, {s0} @ encoding: [0x90,0xec,0x01,0x0a]
73 # FP32: vpop {{.*}} @ encoding: [0xbd,0xec,0x20,0x0a]
77 # FP32: vpop {{.*}} @ encoding: [0xbd,0xec,0x20,0x0a]
81 # FP32: vstmia r0, {s0} @ encoding: [0x80,0xec,0x01,0x0a]
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/
D2013-11-18-fp64-const0.ll2 ; RUN: llc < %s -mtriple=mips-- -mattr=-fp64 | FileCheck %s -check-prefix=CHECK-FP32
14 ; CHECK-FP32-LABEL: autogen_SD3718491962:
15 ; CHECK-FP32: # %bb.0: # %BB
16 ; CHECK-FP32-NEXT: lui $1, %hi($CPI0_0)
17 ; CHECK-FP32-NEXT: ldc1 $f0, %lo($CPI0_0)($1)
18 ; CHECK-FP32-NEXT: mtc1 $zero, $f2
19 ; CHECK-FP32-NEXT: mtc1 $zero, $f3
20 ; CHECK-FP32-NEXT: $BB0_1: # %CF88
21 ; CHECK-FP32-NEXT: # =>This Inner Loop Header: Depth=1
22 ; CHECK-FP32-NEXT: c.ueq.d $f12, $f0
[all …]

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