Home
last modified time | relevance | path

Searched refs:FP64 (Results 1 – 25 of 112) sorted by relevance

12345

/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/
Dfloat_args.ll4 …bal-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
14 ; FP64-LABEL: name: float_in_fpr
15 ; FP64: bb.1.entry:
16 ; FP64: liveins: $f12, $f14
17 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
18 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
19 ; FP64: $f0 = COPY [[COPY1]](s32)
20 ; FP64: RetRA implicit $f0
33 ; FP64-LABEL: name: double_in_fpr
34 ; FP64: bb.1.entry:
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZInstrHFP.td23 def LTDR : UnaryRR <"ltdr", 0x22, null_frag, FP64, FP64>;
32 def LEDR : UnaryRR <"ledr", 0x35, null_frag, FP32, FP64>;
34 def LDXR : UnaryRR <"ldxr", 0x25, null_frag, FP64, FP128>;
36 def LRER : UnaryRR <"lrer", 0x35, null_frag, FP32, FP64>;
37 def LRDR : UnaryRR <"lrdr", 0x25, null_frag, FP64, FP128>;
41 def LDER : UnaryRRE<"lder", 0xB324, null_frag, FP64, FP32>;
43 def LXDR : UnaryRRE<"lxdr", 0xB325, null_frag, FP128, FP64>;
45 def LDE : UnaryRXE<"lde", 0xED24, null_frag, FP64, 4>;
51 def CDFR : UnaryRRE<"cdfr", 0xB3B5, null_frag, FP64, GR32>;
55 def CDGR : UnaryRRE<"cdgr", 0xB3C5, null_frag, FP64, GR64>;
[all …]
DSystemZInstrDFP.td23 def LTDTR : UnaryRRE<"ltdtr", 0xB3D6, null_frag, FP64, FP64>;
35 def LEDTR : TernaryRRFe<"ledtr", 0xB3D5, FP32, FP64>;
41 def LDETR : BinaryRRFd<"ldetr", 0xB3D4, FP64, FP32>;
42 def LXDTR : BinaryRRFd<"lxdtr", 0xB3DC, FP128, FP64>;
47 def CDGTR : UnaryRRE<"cdgtr", 0xB3F1, null_frag, FP64, GR64>;
50 def CDGTRA : TernaryRRFe<"cdgtra", 0xB3F1, FP64, GR64>;
52 def CDFTR : TernaryRRFe<"cdftr", 0xB951, FP64, GR32>;
59 def CDLGTR : TernaryRRFe<"cdlgtr", 0xB952, FP64, GR64>;
61 def CDLFTR : TernaryRRFe<"cdlftr", 0xB953, FP64, GR32>;
67 def CGDTR : BinaryRRFe<"cgdtr", 0xB3E1, GR64, FP64>;
[all …]
DSystemZInstrFP.td22 def SelectF64 : SelectWrapper<f64, FP64>;
30 defm CondStoreF64 : CondStores<FP64, simple_store,
40 def LZDR : InherentRRE<"lzdr", 0xB375, FP64, fpimm0>;
46 def LDR : UnaryRR <"ldr", 0x28, null_frag, FP64, FP64>;
58 defm LTDBR : LoadAndTestRRE<"ltdbr", 0xB312, FP64>;
66 defm : CompareZeroFP<LTDBRCompare, FP64>;
75 def LTDBRCompare_VecPseudo : Pseudo<(outs), (ins FP64:$R1, FP64:$R2), []>;
80 defm : CompareZeroFP<LTDBRCompare_VecPseudo, FP64>;
86 def LGDR : UnaryRRE<"lgdr", 0xB3CD, bitconvert, GR64, FP64>;
87 def LDGR : UnaryRRE<"ldgr", 0xB3C1, bitconvert, FP64, GR64>;
[all …]
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZInstrHFP.td23 def LTDR : UnaryRR <"ltdr", 0x22, null_frag, FP64, FP64>;
32 def LEDR : UnaryRR <"ledr", 0x35, null_frag, FP32, FP64>;
34 def LDXR : UnaryRR <"ldxr", 0x25, null_frag, FP64, FP128>;
36 def LRER : UnaryRR <"lrer", 0x35, null_frag, FP32, FP64>;
37 def LRDR : UnaryRR <"lrdr", 0x25, null_frag, FP64, FP128>;
41 def LDER : UnaryRRE<"lder", 0xB324, null_frag, FP64, FP32>;
43 def LXDR : UnaryRRE<"lxdr", 0xB325, null_frag, FP128, FP64>;
45 def LDE : UnaryRXE<"lde", 0xED24, null_frag, FP64, 4>;
51 def CDFR : UnaryRRE<"cdfr", 0xB3B5, null_frag, FP64, GR32>;
55 def CDGR : UnaryRRE<"cdgr", 0xB3C5, null_frag, FP64, GR64>;
[all …]
DSystemZInstrDFP.td23 def LTDTR : UnaryRRE<"ltdtr", 0xB3D6, null_frag, FP64, FP64>;
35 def LEDTR : TernaryRRFe<"ledtr", 0xB3D5, FP32, FP64>;
41 def LDETR : BinaryRRFd<"ldetr", 0xB3D4, FP64, FP32>;
42 def LXDTR : BinaryRRFd<"lxdtr", 0xB3DC, FP128, FP64>;
47 def CDGTR : UnaryRRE<"cdgtr", 0xB3F1, null_frag, FP64, GR64>;
50 def CDGTRA : TernaryRRFe<"cdgtra", 0xB3F1, FP64, GR64>;
52 def CDFTR : TernaryRRFe<"cdftr", 0xB951, FP64, GR32>;
59 def CDLGTR : TernaryRRFe<"cdlgtr", 0xB952, FP64, GR64>;
61 def CDLFTR : TernaryRRFe<"cdlftr", 0xB953, FP64, GR32>;
67 def CGDTR : BinaryRRFe<"cgdtr", 0xB3E1, GR64, FP64>;
[all …]
DSystemZInstrFP.td22 def SelectF64 : SelectWrapper<f64, FP64>;
30 defm CondStoreF64 : CondStores<FP64, simple_store,
40 def LZDR : InherentRRE<"lzdr", 0xB375, FP64, fpimm0>;
46 def LDR : UnaryRR <"ldr", 0x28, null_frag, FP64, FP64>;
58 defm LTDBR : LoadAndTestRRE<"ltdbr", 0xB312, FP64>;
66 defm : CompareZeroFP<LTDBRCompare, FP64>;
75 def LTDBRCompare_VecPseudo : Pseudo<(outs), (ins FP64:$R1, FP64:$R2), []>;
80 defm : CompareZeroFP<LTDBRCompare_VecPseudo, FP64>;
86 def LGDR : UnaryRRE<"lgdr", 0xB3CD, bitconvert, GR64, FP64>;
87 def LDGR : UnaryRRE<"ldgr", 0xB3C1, bitconvert, FP64, GR64>;
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
Dfptosi_and_fptoui.mir3 …p64,+mips32r2 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
44 ; FP64-LABEL: name: f32toi64
45 ; FP64: liveins: $f12
46 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
47 ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
48 ; FP64: $f12 = COPY [[COPY]](s32)
49 …; FP64: JAL &__fixsfdi, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-…
50 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
51 ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
52 ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
[all …]
Dsitofp_and_uitofp.mir3 …p64,+mips32r2 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
44 ; FP64-LABEL: name: i64tof32
45 ; FP64: liveins: $a0, $a1
46 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
47 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
48 ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
49 ; FP64: $a0 = COPY [[COPY]](s32)
50 ; FP64: $a1 = COPY [[COPY1]](s32)
51 …; FP64: JAL &__floatdisf, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $a0, implicit…
52 ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY $f0
[all …]
Dfloat_arithmetic_operations.mir3 …p64,+mips32r2 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
32 ; FP64-LABEL: name: float_add
33 ; FP64: liveins: $f12, $f14
34 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
35 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
36 ; FP64: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]
37 ; FP64: $f0 = COPY [[FADD]](s32)
38 ; FP64: RetRA implicit $f0
61 ; FP64-LABEL: name: float_sub
62 ; FP64: liveins: $f12, $f14
[all …]
Dceil_and_floor.mir3 …p64,+mips32r2 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
30 ; FP64-LABEL: name: ceil_f32
31 ; FP64: liveins: $f12
32 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
33 ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
34 ; FP64: $f12 = COPY [[COPY]](s32)
35 …; FP64: JAL &ceilf, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def …
36 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f0
37 ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
38 ; FP64: $f0 = COPY [[COPY1]](s32)
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
Dfcmp.mir3 …32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
56 ; FP64-LABEL: name: false_s
57 ; FP64: liveins: $f12, $f14
58 ; FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0
59 ; FP64: $v0 = COPY [[ORi]]
60 ; FP64: RetRA implicit $v0
82 ; FP64-LABEL: name: true_s
83 ; FP64: liveins: $f12, $f14
84 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
85 ; FP64: $v0 = COPY [[ADDiu]]
[all …]
Dfloat_arithmetic_operations.mir3 …32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
33 ; FP64-LABEL: name: float_add
34 ; FP64: liveins: $f12, $f14
35 ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
36 ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
37 ; FP64: [[FADD_S:%[0-9]+]]:fgr32 = FADD_S [[COPY]], [[COPY1]]
38 ; FP64: $f0 = COPY [[FADD_S]]
39 ; FP64: RetRA implicit $f0
64 ; FP64-LABEL: name: float_sub
65 ; FP64: liveins: $f12, $f14
[all …]
Dfloat_args.mir3 …32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
31 ; FP64-LABEL: name: float_in_fpr
32 ; FP64: liveins: $f12, $f14
33 ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f14
34 ; FP64: $f0 = COPY [[COPY]]
35 ; FP64: RetRA implicit $f0
56 ; FP64-LABEL: name: double_in_fpr
57 ; FP64: liveins: $d6, $d7
58 ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d7
59 ; FP64: $d0 = COPY [[COPY]]
[all …]
Dsitofp_and_uitofp.mir3 …32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
27 ; FP64-LABEL: name: i32tof32
28 ; FP64: liveins: $a0
29 ; FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
30 ; FP64: [[PseudoCVT_S_W:%[0-9]+]]:fgr32 = PseudoCVT_S_W [[COPY]]
31 ; FP64: $f0 = COPY [[PseudoCVT_S_W]]
32 ; FP64: RetRA implicit $f0
55 ; FP64-LABEL: name: i32tof64
56 ; FP64: liveins: $a0
57 ; FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
[all …]
Dfloat_constants.mir3 …32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
24 ; FP64-LABEL: name: e_single_precision
25 ; FP64: [[LUi:%[0-9]+]]:gpr32 = LUi 16429
26 ; FP64: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 63572
27 ; FP64: [[MTC1_:%[0-9]+]]:fgr32 = MTC1 [[ORi]]
28 ; FP64: $f0 = COPY [[MTC1_]]
29 ; FP64: RetRA implicit $f0
51 ; FP64-LABEL: name: e_double_precision
52 ; FP64: [[LUi:%[0-9]+]]:gpr32 = LUi 16389
53 ; FP64: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 48906
[all …]
Dfptosi_and_fptoui.mir3 …32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
27 ; FP64-LABEL: name: f32toi32
28 ; FP64: liveins: $f12
29 ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
30 ; FP64: [[TRUNC_W_S:%[0-9]+]]:fgr32 = TRUNC_W_S [[COPY]]
31 ; FP64: [[MFC1_:%[0-9]+]]:gpr32 = MFC1 [[TRUNC_W_S]]
32 ; FP64: $v0 = COPY [[MFC1_]]
33 ; FP64: RetRA implicit $v0
57 ; FP64-LABEL: name: f64toi32
58 ; FP64: liveins: $d6
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/
Dsitofp_and_uitofp.ll3 …fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64
155 ; FP64-LABEL: u32tof32:
156 ; FP64: # %bb.0: # %entry
157 ; FP64-NEXT: lui $1, 17200
158 ; FP64-NEXT: mtc1 $4, $f0
159 ; FP64-NEXT: mthc1 $1, $f0
160 ; FP64-NEXT: lui $2, 17200
161 ; FP64-NEXT: ori $1, $zero, 0
162 ; FP64-NEXT: mtc1 $1, $f1
163 ; FP64-NEXT: mthc1 $2, $f1
[all …]
Dfptosi_and_fptoui.ll3 …fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64
253 ; FP64-LABEL: f64tou32:
254 ; FP64: # %bb.0: # %entry
255 ; FP64-NEXT: trunc.w.d $f0, $f12
256 ; FP64-NEXT: mfc1 $1, $f0
257 ; FP64-NEXT: lui $3, 16864
258 ; FP64-NEXT: ori $2, $zero, 0
259 ; FP64-NEXT: mtc1 $2, $f0
260 ; FP64-NEXT: mthc1 $3, $f0
261 ; FP64-NEXT: sub.d $f1, $f12, $f0
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
Dfloat_arithmetic_operations.mir3 …+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
33 ; FP64-LABEL: name: float_add
34 ; FP64: liveins: $f12, $f14
35 ; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
36 ; FP64: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
37 ; FP64: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[COPY]], [[COPY1]]
38 ; FP64: $f0 = COPY [[FADD]](s32)
39 ; FP64: RetRA implicit $f0
63 ; FP64-LABEL: name: float_sub
64 ; FP64: liveins: $f12, $f14
[all …]
Dfloat_args.mir3 …+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
31 ; FP64-LABEL: name: float_in_fpr
32 ; FP64: liveins: $f12, $f14
33 ; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f14
34 ; FP64: $f0 = COPY [[COPY]](s32)
35 ; FP64: RetRA implicit $f0
55 ; FP64-LABEL: name: double_in_fpr
56 ; FP64: liveins: $d6, $d7
57 ; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d7
58 ; FP64: $d0 = COPY [[COPY]](s64)
[all …]
Dsitofp_and_uitofp.mir3 …+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
26 ; FP64-LABEL: name: i32tof32
27 ; FP64: liveins: $a0
28 ; FP64: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
29 ; FP64: [[SITOFP:%[0-9]+]]:fprb(s32) = G_SITOFP [[COPY]](s32)
30 ; FP64: $f0 = COPY [[SITOFP]](s32)
31 ; FP64: RetRA implicit $f0
53 ; FP64-LABEL: name: i32tof64
54 ; FP64: liveins: $a0
55 ; FP64: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
[all …]
Dfcmp.mir3 …+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
27 ; FP64-LABEL: name: oeq_s
28 ; FP64: liveins: $f12, $f14
29 ; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
30 ; FP64: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
31 ; FP64: [[FCMP:%[0-9]+]]:gprb(s32) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]]
32 ; FP64: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[FCMP]](s32)
33 ; FP64: $v0 = COPY [[COPY2]](s32)
34 ; FP64: RetRA implicit $v0
60 ; FP64-LABEL: name: oeq_d
[all …]
/external/llvm/lib/Target/SystemZ/
DSystemZInstrFP.td16 def SelectF64 : SelectWrapper<FP64>;
21 defm CondStoreF64 : CondStores<FP64, nonvolatile_store,
31 def LZDR : InherentRRE<"lzdr", 0xB375, FP64, (fpimm0)>;
38 def LDR : UnaryRR <"ld", 0x28, null_frag, FP64, FP64>;
50 defm LTDBR : LoadAndTestRRE<"ltdb", 0xB312, FP64>;
58 defm : CompareZeroFP<LTDBRCompare, FP64>;
66 def LTDBRCompare_VecPseudo : Pseudo<(outs), (ins FP64:$R1, FP64:$R2), []>;
71 defm : CompareZeroFP<LTDBRCompare_VecPseudo, FP64>;
76 def LGDR : UnaryRRE<"lgd", 0xB3CD, bitconvert, GR64, FP64>;
77 def LDGR : UnaryRRE<"ldg", 0xB3C1, bitconvert, FP64, GR64>;
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/
D2013-11-18-fp64-const0.ll3 ; RUN: llc < %s -mtriple=mips-- -mcpu=mips32r2 -mattr=+fp64 | FileCheck %s -check-prefix=CHECK-FP64
7 ; It originally failed on MIPS32 with FP64 with the following error:
35 ; CHECK-FP64-LABEL: autogen_SD3718491962:
36 ; CHECK-FP64: # %bb.0: # %BB
37 ; CHECK-FP64-NEXT: lui $1, %hi($CPI0_0)
38 ; CHECK-FP64-NEXT: ldc1 $f0, %lo($CPI0_0)($1)
39 ; CHECK-FP64-NEXT: mtc1 $zero, $f1
40 ; CHECK-FP64-NEXT: mthc1 $zero, $f1
41 ; CHECK-FP64-NEXT: $BB0_1: # %CF88
42 ; CHECK-FP64-NEXT: # =>This Inner Loop Header: Depth=1
[all …]

12345