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Searched refs:FPCR (Results 1 – 25 of 27) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AArch64/
Darm64-fpcr.ll5 ; CHECK: mrs x0, FPCR
15 ; CHECK: mrs x8, FPCR
/external/OpenCSD/decoder/tests/snapshots/a55-test-tpiu/
Ddevice1.ini252 FPCR=0x00000000 key
/external/OpenCSD/decoder/tests/snapshots/a57_single_step/
Ddevice1.ini252 FPCR=0x00000000 key
/external/vixl/test/aarch64/
Dtest-assembler-fp-aarch64.cc5066 __ Mrs(x0, FPCR); in DefaultNaNHelper()
5068 __ Msr(FPCR, x1); in DefaultNaNHelper()
5107 __ Msr(FPCR, x0); in DefaultNaNHelper()
5194 __ Mrs(x0, FPCR); in DefaultNaNHelper()
5196 __ Msr(FPCR, x1); in DefaultNaNHelper()
5235 __ Msr(FPCR, x0); in DefaultNaNHelper()
Dtest-assembler-aarch64.cc6590 __ Mrs(x6, FPCR); in TEST()
6770 __ Msr(FPCR, x8); in TEST()
6771 __ Mrs(x8, FPCR); in TEST()
6789 __ Msr(FPCR, x9); in TEST()
6790 __ Mrs(x9, FPCR); in TEST()
6798 __ Msr(FPCR, x10); in TEST()
6799 __ Mrs(x10, FPCR); in TEST()
Dtest-disasm-aarch64.cc2529 COMPARE(mrs(x15, FPCR), "mrs x15, fpcr"); in TEST()
2546 COMPARE(msr(FPCR, x15), "msr fpcr, x15"); in TEST()
Dtest-cpu-features-aarch64.cc379 TEST_NONE(mrs_0, mrs(x0, FPCR))
380 TEST_NONE(msr_0, msr(FPCR, x0))
/external/vixl/src/aarch64/
Dsimulator-aarch64.cc61 case FPCR: in DefaultValueFor()
126 fpcr_ = SimSystemRegister::DefaultValueFor(FPCR); in ResetSystemRegisters()
801 PrintSystemRegister(FPCR); in PrintSystemRegisters()
1197 case FPCR: { in PrintSystemRegister()
4535 case FPCR: in VisitSystem()
4562 case FPCR: in VisitSystem()
4564 LogSystemRegister(FPCR); in VisitSystem()
Dconstants-aarch64.h239 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask)
501 FPCR = SystemRegisterEncoder<3, 3, 4, 4, 0>::value, enumerator
Ddisasm-aarch64.cc10301 case FPCR: in SubstituteImmediateField()
Dassembler-aarch64.cc6232 case FPCR: in CPUHas()
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenSystemOperands.inc433 FPCR = 55840,
2497 { "FPCR", 0xDA20, true, true, {} }, // 243
3258 { "FPCR", 243 },
/external/llvm-project/llvm/test/MC/AArch64/
Dbasic-a64-instructions.s3813 msr FPCR, x12
4361 mrs x9, FPCR
/external/llvm/test/MC/AArch64/
Dbasic-a64-instructions.s3827 msr FPCR, x12
4375 mrs x9, FPCR
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsicsAArch64.td617 // FPCR
/external/llvm-project/llvm/include/llvm/IR/
DIntrinsicsAArch64.td664 // FPCR
/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td578 def : RWSysReg<"FPCR", 0b11, 0b011, 0b0100, 0b0100, 0b000>;
/external/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt3300 # CHECK: msr {{fpcr|FPCR}}, x12
3592 # CHECK: mrs x9, {{fpcr|FPCR}}
/external/llvm-project/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt3287 # CHECK: msr {{fpcr|FPCR}}, x12
3581 # CHECK: mrs x9, {{fpcr|FPCR}}
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td852 def : RWSysReg<"FPCR", 0b11, 0b011, 0b0100, 0b0100, 0b000>;
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td857 def : RWSysReg<"FPCR", 0b11, 0b011, 0b0100, 0b0100, 0b000>;
DAArch64InstrInfo.td1136 // FPCR register
/external/OpenCSD/decoder/tests/snapshots/juno_r1_1/ds-5-dumps/
DTrace_Report_0x15_cpu_5_2015Sep17_105126.txt386 EL1N:0xFFFFFFC000084EF8 D53B4408 MRS x8,FPCR
3229 EL1N:0xFFFFFFC000084EF8 D53B4408 MRS x8,FPCR
/external/llvm-project/clang/unittests/Format/
DFormatTest.cpp16723 asm volatile("mrs %x[result], FPCR" : [result] "=r"(result)); in TEST_F()
/external/OpenCSD/decoder/tests/snapshots-ete/ete_mem/bindir/
DOTHERS_exec560 …VAE3OS��������TLBI_RVALE3OS�������TLBI_RVAE3����������TLBI_RVALE3���������FPCR����������������FPSR…

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