/external/llvm-project/llvm/test/CodeGen/AArch64/ |
D | arm64-fpcr.ll | 5 ; CHECK: mrs x0, FPCR 15 ; CHECK: mrs x8, FPCR
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/external/OpenCSD/decoder/tests/snapshots/a55-test-tpiu/ |
D | device1.ini | 252 FPCR=0x00000000 key
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/external/OpenCSD/decoder/tests/snapshots/a57_single_step/ |
D | device1.ini | 252 FPCR=0x00000000 key
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/external/vixl/test/aarch64/ |
D | test-assembler-fp-aarch64.cc | 5066 __ Mrs(x0, FPCR); in DefaultNaNHelper() 5068 __ Msr(FPCR, x1); in DefaultNaNHelper() 5107 __ Msr(FPCR, x0); in DefaultNaNHelper() 5194 __ Mrs(x0, FPCR); in DefaultNaNHelper() 5196 __ Msr(FPCR, x1); in DefaultNaNHelper() 5235 __ Msr(FPCR, x0); in DefaultNaNHelper()
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D | test-assembler-aarch64.cc | 6590 __ Mrs(x6, FPCR); in TEST() 6770 __ Msr(FPCR, x8); in TEST() 6771 __ Mrs(x8, FPCR); in TEST() 6789 __ Msr(FPCR, x9); in TEST() 6790 __ Mrs(x9, FPCR); in TEST() 6798 __ Msr(FPCR, x10); in TEST() 6799 __ Mrs(x10, FPCR); in TEST()
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D | test-disasm-aarch64.cc | 2529 COMPARE(mrs(x15, FPCR), "mrs x15, fpcr"); in TEST() 2546 COMPARE(msr(FPCR, x15), "msr fpcr, x15"); in TEST()
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D | test-cpu-features-aarch64.cc | 379 TEST_NONE(mrs_0, mrs(x0, FPCR)) 380 TEST_NONE(msr_0, msr(FPCR, x0))
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/external/vixl/src/aarch64/ |
D | simulator-aarch64.cc | 61 case FPCR: in DefaultValueFor() 126 fpcr_ = SimSystemRegister::DefaultValueFor(FPCR); in ResetSystemRegisters() 801 PrintSystemRegister(FPCR); in PrintSystemRegisters() 1197 case FPCR: { in PrintSystemRegister() 4535 case FPCR: in VisitSystem() 4562 case FPCR: in VisitSystem() 4564 LogSystemRegister(FPCR); in VisitSystem()
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D | constants-aarch64.h | 239 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask) 501 FPCR = SystemRegisterEncoder<3, 3, 4, 4, 0>::value, enumerator
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D | disasm-aarch64.cc | 10301 case FPCR: in SubstituteImmediateField()
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D | assembler-aarch64.cc | 6232 case FPCR: in CPUHas()
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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
D | AArch64GenSystemOperands.inc | 433 FPCR = 55840, 2497 { "FPCR", 0xDA20, true, true, {} }, // 243 3258 { "FPCR", 243 },
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/external/llvm-project/llvm/test/MC/AArch64/ |
D | basic-a64-instructions.s | 3813 msr FPCR, x12 4361 mrs x9, FPCR
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/external/llvm/test/MC/AArch64/ |
D | basic-a64-instructions.s | 3827 msr FPCR, x12 4375 mrs x9, FPCR
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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
D | IntrinsicsAArch64.td | 617 // FPCR
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/external/llvm-project/llvm/include/llvm/IR/ |
D | IntrinsicsAArch64.td | 664 // FPCR
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/external/llvm/lib/Target/AArch64/ |
D | AArch64SystemOperands.td | 578 def : RWSysReg<"FPCR", 0b11, 0b011, 0b0100, 0b0100, 0b000>;
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/external/llvm/test/MC/Disassembler/AArch64/ |
D | basic-a64-instructions.txt | 3300 # CHECK: msr {{fpcr|FPCR}}, x12 3592 # CHECK: mrs x9, {{fpcr|FPCR}}
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/external/llvm-project/llvm/test/MC/Disassembler/AArch64/ |
D | basic-a64-instructions.txt | 3287 # CHECK: msr {{fpcr|FPCR}}, x12 3581 # CHECK: mrs x9, {{fpcr|FPCR}}
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64SystemOperands.td | 852 def : RWSysReg<"FPCR", 0b11, 0b011, 0b0100, 0b0100, 0b000>;
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/external/llvm-project/llvm/lib/Target/AArch64/ |
D | AArch64SystemOperands.td | 857 def : RWSysReg<"FPCR", 0b11, 0b011, 0b0100, 0b0100, 0b000>;
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D | AArch64InstrInfo.td | 1136 // FPCR register
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/external/OpenCSD/decoder/tests/snapshots/juno_r1_1/ds-5-dumps/ |
D | Trace_Report_0x15_cpu_5_2015Sep17_105126.txt | 386 EL1N:0xFFFFFFC000084EF8 D53B4408 MRS x8,FPCR 3229 EL1N:0xFFFFFFC000084EF8 D53B4408 MRS x8,FPCR
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/external/llvm-project/clang/unittests/Format/ |
D | FormatTest.cpp | 16723 asm volatile("mrs %x[result], FPCR" : [result] "=r"(result)); in TEST_F()
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/external/OpenCSD/decoder/tests/snapshots-ete/ete_mem/bindir/ |
D | OTHERS_exec | 560 …VAE3OSTLBI_RVALE3OSTLBI_RVAE3TLBI_RVALE3FPCRFPSR…
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