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Searched refs:FPDiff (Results 1 – 20 of 20) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64CallLowering.cpp134 int FPDiff = 0) in OutgoingArgHandler()
136 AssignFnVarArg(AssignFnVarArg), IsTailCall(IsTailCall), FPDiff(FPDiff), in OutgoingArgHandler()
148 Offset += FPDiff; in getStackAddress()
210 int FPDiff; member
831 int FPDiff = 0; in lowerTailCall() local
853 FPDiff = NumReusableBytes - NumBytes; in lowerTailCall()
860 assert(FPDiff % 16 == 0 && "unaligned stack on tail call"); in lowerTailCall()
868 AssignFnVarArg, true, FPDiff); in lowerTailCall()
896 MIB->getOperand(1).setImm(FPDiff); in lowerTailCall()
DAArch64InstrInfo.td7176 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff), []>,
7178 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>,
7184 def TCRETURNriALL : Pseudo<(outs), (ins GPR64:$dst, i32imm:$FPDiff), []>,
7188 def TCRETURNriBTI : Pseudo<(outs), (ins rtcGPR64:$dst, i32imm:$FPDiff), []>,
7192 def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)),
7193 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>,
7195 def : Pat<(AArch64tcret rtcGPR64:$dst, (i32 timm:$FPDiff)),
7196 (TCRETURNriBTI rtcGPR64:$dst, imm:$FPDiff)>,
7198 def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)),
7199 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
[all …]
DAArch64ISelLowering.cpp4012 int FPDiff = 0; in LowerCall() local
4024 FPDiff = NumReusableBytes - NumBytes; in LowerCall()
4031 assert(FPDiff % 16 == 0 && "unaligned stack on tail call"); in LowerCall()
4161 Offset = Offset + FPDiff; in LowerCall()
4260 Ops.push_back(DAG.getTargetConstant(FPDiff, DL, MVT::i32)); in LowerCall()
/external/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64CallLowering.cpp136 int FPDiff = 0) in OutgoingArgHandler()
138 AssignFnVarArg(AssignFnVarArg), IsTailCall(IsTailCall), FPDiff(FPDiff), in OutgoingArgHandler()
148 Offset += FPDiff; in getStackAddress()
225 int FPDiff; member
856 int FPDiff = 0; in lowerTailCall() local
878 FPDiff = NumReusableBytes - NumBytes; in lowerTailCall()
885 assert(FPDiff % 16 == 0 && "unaligned stack on tail call"); in lowerTailCall()
892 AssignFnVarArg, true, FPDiff); in lowerTailCall()
920 MIB->getOperand(1).setImm(FPDiff); in lowerTailCall()
/external/llvm/lib/Target/X86/
DX86RegisterInfo.cpp227 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0; in getRegPressureLimit() local
232 return 4 - FPDiff; in getRegPressureLimit()
234 return 12 - FPDiff; in getRegPressureLimit()
DX86ISelLowering.h1058 bool Is64Bit, int FPDiff,
DX86ISelLowering.cpp2916 bool Is64Bit, int FPDiff, const SDLoc &dl) const { in EmitTailCallLoadRetAddr() argument
2932 int FPDiff, const SDLoc &dl) { in EmitTailCallStoreRetAddr() argument
2934 if (!FPDiff) return Chain; in EmitTailCallStoreRetAddr()
2937 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize, in EmitTailCallStoreRetAddr()
3045 int FPDiff = 0; in LowerCall() local
3050 FPDiff = NumBytesCallerPushed - NumBytes; in LowerCall()
3054 if (FPDiff < X86Info->getTCReturnAddrDelta()) in LowerCall()
3055 X86Info->setTCReturnAddrDelta(FPDiff); in LowerCall()
3080 if (isTailCall && FPDiff) in LowerCall()
3082 Is64Bit, FPDiff, dl); in LowerCall()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86RegisterInfo.cpp264 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0; in getRegPressureLimit() local
269 return 4 - FPDiff; in getRegPressureLimit()
271 return 12 - FPDiff; in getRegPressureLimit()
DX86ISelLowering.h1335 bool Is64Bit, int FPDiff,
DX86ISelLowering.cpp3736 bool Is64Bit, int FPDiff, const SDLoc &dl) const { in EmitTailCallLoadRetAddr() argument
3751 int FPDiff, const SDLoc &dl) { in EmitTailCallStoreRetAddr() argument
3753 if (!FPDiff) return Chain; in EmitTailCallStoreRetAddr()
3756 MF.getFrameInfo().CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize, in EmitTailCallStoreRetAddr()
3876 int FPDiff = 0; in LowerCall() local
3881 FPDiff = NumBytesCallerPushed - NumBytes; in LowerCall()
3885 if (FPDiff < X86Info->getTCReturnAddrDelta()) in LowerCall()
3886 X86Info->setTCReturnAddrDelta(FPDiff); in LowerCall()
3911 if (isTailCall && FPDiff) in LowerCall()
3913 Is64Bit, FPDiff, dl); in LowerCall()
[all …]
/external/llvm-project/llvm/lib/Target/X86/
DX86RegisterInfo.cpp259 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0; in getRegPressureLimit() local
264 return 4 - FPDiff; in getRegPressureLimit()
266 return 12 - FPDiff; in getRegPressureLimit()
DX86ISelLowering.h1466 bool Is64Bit, int FPDiff,
DX86ISelLowering.cpp3819 bool Is64Bit, int FPDiff, const SDLoc &dl) const { in EmitTailCallLoadRetAddr() argument
3834 int FPDiff, const SDLoc &dl) { in EmitTailCallStoreRetAddr() argument
3836 if (!FPDiff) return Chain; in EmitTailCallStoreRetAddr()
3839 MF.getFrameInfo().CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize, in EmitTailCallStoreRetAddr()
3959 int FPDiff = 0; in LowerCall() local
3964 FPDiff = NumBytesCallerPushed - NumBytes; in LowerCall()
3968 if (FPDiff < X86Info->getTCReturnAddrDelta()) in LowerCall()
3969 X86Info->setTCReturnAddrDelta(FPDiff); in LowerCall()
4009 if (isTailCall && FPDiff) in LowerCall()
4011 Is64Bit, FPDiff, dl); in LowerCall()
[all …]
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUCallLowering.cpp194 int FPDiff; member
204 bool IsTailCall = false, int FPDiff = 0) in AMDGPUOutgoingArgHandler()
206 AssignFnVarArg(AssignFnVarArg), FPDiff(FPDiff), IsTailCall(IsTailCall) { in AMDGPUOutgoingArgHandler()
DSIISelLowering.cpp3008 int32_t FPDiff = 0; in LowerCall() local
3083 Offset = Offset + FPDiff; in LowerCall()
3185 Ops.push_back(DAG.getTargetConstant(FPDiff, DL, MVT::i32)); in LowerCall()
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td7548 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff), []>,
7550 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>,
7556 def TCRETURNriALL : Pseudo<(outs), (ins GPR64:$dst, i32imm:$FPDiff), []>,
7560 def TCRETURNriBTI : Pseudo<(outs), (ins rtcGPR64:$dst, i32imm:$FPDiff), []>,
7564 def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)),
7565 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>,
7567 def : Pat<(AArch64tcret rtcGPR64:$dst, (i32 timm:$FPDiff)),
7568 (TCRETURNriBTI rtcGPR64:$dst, imm:$FPDiff)>,
7570 def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)),
7571 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
[all …]
DAArch64ISelLowering.cpp5199 int FPDiff = 0; in LowerCall() local
5211 FPDiff = NumReusableBytes - NumBytes; in LowerCall()
5218 assert(FPDiff % 16 == 0 && "unaligned stack on tail call"); in LowerCall()
5397 Offset = Offset + FPDiff; in LowerCall()
5496 Ops.push_back(DAG.getTargetConstant(FPDiff, DL, MVT::i32)); in LowerCall()
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td6092 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff), []>,
6094 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>,
6098 def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)),
6099 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>;
6100 def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)),
6101 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
6102 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
6103 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
DAArch64ISelLowering.cpp3013 int FPDiff = 0; in LowerCall() local
3025 FPDiff = NumReusableBytes - NumBytes; in LowerCall()
3032 assert(FPDiff % 16 == 0 && "unaligned stack on tail call"); in LowerCall()
3116 Offset = Offset + FPDiff; in LowerCall()
3219 Ops.push_back(DAG.getTargetConstant(FPDiff, DL, MVT::i32)); in LowerCall()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp2768 int32_t FPDiff = 0; in LowerCall() local
2843 Offset = Offset + FPDiff; in LowerCall()
2938 Ops.push_back(DAG.getTargetConstant(FPDiff, DL, MVT::i32)); in LowerCall()