/external/elfutils/backends/ |
D | s390_corenote.c | 66 #define FPR(at, n, dwreg) \ macro 71 FPR (1 + 0, 1, 16), /* f0 */ 72 FPR (1 + 1, 1, 20), /* f1 */ 73 FPR (1 + 2, 1, 17), /* f2 */ 74 FPR (1 + 3, 1, 21), /* f3 */ 75 FPR (1 + 4, 1, 18), /* f4 */ 76 FPR (1 + 5, 1, 22), /* f5 */ 77 FPR (1 + 6, 1, 19), /* f6 */ 78 FPR (1 + 7, 1, 23), /* f7 */ 79 FPR (1 + 8, 1, 24), /* f8 */ [all …]
|
/external/llvm-project/llvm/lib/Target/AArch64/ |
D | AArch64GenRegisterBankInfo.def | 16 // 0: FPR 16-bit value. 18 // 1: FPR 32-bit value. 20 // 2: FPR 64-bit value. 22 // 3: FPR 128-bit value. 24 // 4: FPR 256-bit value. 26 // 5: FPR 512-bit value. 41 // 1: FPR 16-bit value. <-- This must match First3OpsIdx. 45 // 4: FPR 32-bit value. <-- This must match First3OpsIdx. 49 // 7: FPR 64-bit value. 53 // 10: FPR 128-bit value. [all …]
|
D | AArch64RegisterBanks.td | 16 def FPRRegBank : RegisterBank<"FPR", [QQQQ]>;
|
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64GenRegisterBankInfo.def | 16 // 0: FPR 16-bit value. 18 // 1: FPR 32-bit value. 20 // 2: FPR 64-bit value. 22 // 3: FPR 128-bit value. 24 // 4: FPR 256-bit value. 26 // 5: FPR 512-bit value. 41 // 1: FPR 16-bit value. <-- This must match First3OpsIdx. 45 // 4: FPR 32-bit value. <-- This must match First3OpsIdx. 49 // 7: FPR 64-bit value. 53 // 10: FPR 128-bit value. [all …]
|
D | AArch64RegisterBankInfo.cpp | 124 CHECK_VALUEMAP(FPR, 16); in AArch64RegisterBankInfo() 125 CHECK_VALUEMAP(FPR, 32); in AArch64RegisterBankInfo() 126 CHECK_VALUEMAP(FPR, 64); in AArch64RegisterBankInfo() 127 CHECK_VALUEMAP(FPR, 128); in AArch64RegisterBankInfo() 128 CHECK_VALUEMAP(FPR, 256); in AArch64RegisterBankInfo() 129 CHECK_VALUEMAP(FPR, 512); in AArch64RegisterBankInfo() 142 CHECK_VALUEMAP_3OPS(FPR, 32); in AArch64RegisterBankInfo() 143 CHECK_VALUEMAP_3OPS(FPR, 64); in AArch64RegisterBankInfo() 144 CHECK_VALUEMAP_3OPS(FPR, 128); in AArch64RegisterBankInfo() 145 CHECK_VALUEMAP_3OPS(FPR, 256); in AArch64RegisterBankInfo() [all …]
|
D | AArch64RegisterBanks.td | 16 def FPRRegBank : RegisterBank<"FPR", [QQQQ]>;
|
/external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
D | AArch64RegisterBankInfo.cpp | 125 CHECK_VALUEMAP(FPR, 16); in AArch64RegisterBankInfo() 126 CHECK_VALUEMAP(FPR, 32); in AArch64RegisterBankInfo() 127 CHECK_VALUEMAP(FPR, 64); in AArch64RegisterBankInfo() 128 CHECK_VALUEMAP(FPR, 128); in AArch64RegisterBankInfo() 129 CHECK_VALUEMAP(FPR, 256); in AArch64RegisterBankInfo() 130 CHECK_VALUEMAP(FPR, 512); in AArch64RegisterBankInfo() 143 CHECK_VALUEMAP_3OPS(FPR, 32); in AArch64RegisterBankInfo() 144 CHECK_VALUEMAP_3OPS(FPR, 64); in AArch64RegisterBankInfo() 145 CHECK_VALUEMAP_3OPS(FPR, 128); in AArch64RegisterBankInfo() 146 CHECK_VALUEMAP_3OPS(FPR, 256); in AArch64RegisterBankInfo() [all …]
|
/external/llvm/test/CodeGen/AArch64/GlobalISel/ |
D | arm64-regbankselect.mir | 78 # FPR is used for both floating point and vector registers. 95 # in FPR, but at the use, it should be GPR. 139 # %1 is forced to be into FPR, but its definition actually 247 # Fast mode maps vector instruction on FPR. 269 ; Now, the default mapping says that %0 and %1 need to be in FPR. 273 ; The mapping of G_OR is on FPR. 294 # Fast mode maps vector instruction on FPR. 300 # is the cheapest, but will need one extra copy to materialize %2 into a FPR. 315 ; Now, the default mapping says that %0 and %1 need to be in FPR. 319 ; The mapping of G_OR is on FPR. [all …]
|
/external/llvm/lib/Target/SystemZ/ |
D | SystemZMachineFunctionInfo.h | 52 void setVarArgsFirstFPR(unsigned FPR) { VarArgsFirstFPR = FPR; } in setVarArgsFirstFPR() argument
|
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
D | SystemZMachineFunctionInfo.h | 73 void setVarArgsFirstFPR(unsigned FPR) { VarArgsFirstFPR = FPR; } in setVarArgsFirstFPR() argument
|
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/ |
D | arm64-regbankselect.mir | 135 # FPR is used for both floating point and vector registers. 154 # in FPR, but at the use, it should be GPR. 194 # %1 is forced to be into FPR, but its definition actually 308 ; Now, the default mapping says that %0 and %1 need to be in FPR. 312 ; The mapping of G_OR is on FPR. 341 ; Now, the default mapping says that %0 and %1 need to be in FPR. 345 ; The mapping of G_OR is on FPR. 350 ; We need to keep %2 into FPR because we do not know anything about it. 741 # %0 has been mapped to GPR, we need to repair to match FPR. 780 # %0 has been mapped to GPR, we need to repair to match FPR. [all …]
|
D | regbankselect-unmerge-vec.mir | 14 ; Ensure that the dest regs have FPR since we're unmerging from a vector 38 ; s128 should be treated as an FPR/vector because it can't live on GPR bank.
|
D | regbank-select.mir | 82 ; if we have two FPR inputs and a GPR output, we should do a floating point 115 ; Same idea as the above test. If the output is an FPR, and one of the 116 ; inputs is an FPR, then it's fewer copies to just do a FCSEL.
|
D | regbank-ceil.ll | 4 ; Make sure that we choose a FPR for the G_FCEIL and G_LOAD instead of a GPR.
|
/external/llvm-project/llvm/lib/Target/SystemZ/ |
D | SystemZMachineFunctionInfo.h | 73 void setVarArgsFirstFPR(Register FPR) { VarArgsFirstFPR = FPR; } in setVarArgsFirstFPR() argument
|
/external/llvm/lib/Target/PowerPC/ |
D | PPCRegisterInfo.td | 47 // FPR - One of the 32 64-bit floating-point registers 48 class FPR<bits<5> num, string n> : PPCReg<n> { 53 class QFPR<FPR SubReg, string n> : PPCReg<n> { 76 class VSRL<FPR SubReg, string n> : PPCReg<n> { 115 def F#Index : FPR<Index, "f"#Index>, 126 def QF#Index : QFPR<!cast<FPR>("F"#Index), "q"#Index>, 138 def VSL#Index : VSRL<!cast<FPR>("F"#Index), "vs"#Index>, 139 DwarfRegAlias<!cast<FPR>("F"#Index)>;
|
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
D | PPCRegisterInfo.td | 52 // FPR - One of the 32 64-bit floating-point registers 53 class FPR<bits<5> num, string n> : PPCReg<n> { 58 class QFPR<FPR SubReg, string n> : PPCReg<n> { 81 class VSRL<FPR SubReg, string n> : PPCReg<n> { 123 def F#Index : FPR<Index, "f"#Index>, 137 def QF#Index : QFPR<!cast<FPR>("F"#Index), "q"#Index>, 149 def VSL#Index : VSRL<!cast<FPR>("F"#Index), "vs"#Index>, 150 DwarfRegAlias<!cast<FPR>("F"#Index)>;
|
/external/llvm-project/llvm/docs/GlobalISel/ |
D | GMIR.rst | 108 registers) and FPR (floating point registers). 111 has to happen in FPR and G_ADD has to happen in GPR. However, even though this 113 happen in both GPR and FPR, and which we want depends on who is going to consume 114 the loaded data. Similarly, G_FNEG can happen in both GPR and FPR. If we assign 115 it to FPR, then we'll use floating point negation. However, if we assign it to 126 AArch64 has three main banks. GPR for integer operations, FPR for floating
|
/external/llvm-project/lldb/source/Plugins/Process/Linux/ |
D | NativeRegisterContextLinux_x86_64.cpp | 224 #define REG_CONTEXT_SIZE (GetRegisterInfoInterface().GetGPRSize() + sizeof(FPR)) 287 return sizeof(FPR); in GetXSTATESize() 291 return sizeof(FPR); in GetXSTATESize() 292 return std::max<std::size_t>(ecx, sizeof(FPR)); in GetXSTATESize() 359 m_xstate.reset(static_cast<FPR *>(std::malloc(xstate_size))); in NativeRegisterContextLinux_x86_64() 530 assert((reg_info->byte_offset - m_fctrl_offset_in_userarea) < sizeof(FPR)); in ReadRegister() 646 sizeof(FPR)); in WriteRegister() 743 ::memcpy(dst, m_xstate.get(), sizeof(FPR)); in ReadAllRegisterValues()
|
/external/llvm/lib/Target/Mips/ |
D | MipsRegisterInfo.td | 51 class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>; 157 def F#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>; 161 def F_HI#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>; 167 [!cast<FPR>("F"#!shl(I, 1)), 168 !cast<FPR>("F"#!add(!shl(I, 1), 1))]>; 172 def D#I#_64 : AFPR64<I, "f"#I, [!cast<FPR>("F"#I), !cast<FPR>("F_HI"#I)]>,
|
/external/llvm-project/lldb/source/Plugins/Process/Utility/ |
D | RegisterInfos_i386.h | 28 LLVM_EXTENSION offsetof(FPR, fxsave) + \ 34 LLVM_EXTENSION offsetof(FPR, xsave) + \ 39 LLVM_EXTENSION offsetof(FPR, xsave) + \
|
D | RegisterInfos_ppc64le.h | 15 #define FPR_OFFSET(regname) (offsetof(FPR, regname) + sizeof(GPR)) 16 #define VMX_OFFSET(regname) (offsetof(VMX, regname) + sizeof(GPR) + sizeof(FPR)) 18 (offsetof(VSX, regname) + sizeof(GPR) + sizeof(FPR) + sizeof(VMX)) 353 } FPR; typedef
|
/external/llvm/test/CodeGen/AArch64/ |
D | arm64-fixed-point-scalar-cvt-dagcombine.ll | 5 ; of the value to a GPR and back to and FPR.
|
/external/llvm/test/CodeGen/SystemZ/ |
D | asm-10.ll | 1 ; Test the FPR constraint "f".
|
/external/llvm-project/llvm/test/CodeGen/AArch64/ |
D | arm64-fixed-point-scalar-cvt-dagcombine.ll | 5 ; of the value to a GPR and back to and FPR.
|