| /external/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterBankInfo.cpp | 42 createRegisterBank(AArch64::FPRRegBankID, "FPR"); in AArch64RegisterBankInfo()
45 addRegBankCoverage(AArch64::FPRRegBankID, AArch64::QQQQRegClassID, TRI); in AArch64RegisterBankInfo()
46 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
94 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
143 getRegBank(AArch64::FPRRegBankID)); in getInstrAlternativeMappings()
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| D | AArch64RegisterBankInfo.h | 26 FPRRegBankID = 1, /// Floating Point/Vector Registers: B, H, S, D, Q. enumerator
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenRegisterBank.inc | 14 FPRRegBankID,
94 RegisterBank FPRRegBank(/* ID */ ARM::FPRRegBankID, /* Name */ "FPRB", /* Size */ 128, /* CoveredRe…
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenRegisterBank.inc | 15 FPRRegBankID,
118 RegisterBank FPRRegBank(/* ID */ AArch64::FPRRegBankID, /* Name */ "FPR", /* Size */ 512, /* Covere…
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterBankInfo.cpp | 56 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
241 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
317 getCopyMapping(AArch64::FPRRegBankID, AArch64::FPRRegBankID, Size), in getInstrAlternativeMappings()
322 getCopyMapping(AArch64::FPRRegBankID, AArch64::GPRRegBankID, Size), in getInstrAlternativeMappings()
327 getCopyMapping(AArch64::GPRRegBankID, AArch64::FPRRegBankID, Size), in getInstrAlternativeMappings()
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| D | AArch64InstructionSelector.cpp | 345 if (RB.getID() == AArch64::FPRRegBankID) { in getRegClassForTypeOnBank()
376 if (RegBankID == AArch64::FPRRegBankID) { in getMinClassForRegBank()
506 case AArch64::FPRRegBankID: in selectBinaryOp()
563 case AArch64::FPRRegBankID: in selectLoadStoreUIOp()
605 assert((DstSize <= 64 || DstBank.getID() == AArch64::FPRRegBankID) && in isValidCopy()
1604 if (RB.getID() != AArch64::FPRRegBankID) { in select()
1694 assert(SrcRB.getID() == AArch64::FPRRegBankID && in select()
1695 DstRB.getID() == AArch64::FPRRegBankID && in select()
2088 } else if (DstRB.getID() == AArch64::FPRRegBankID) { in select()
2977 if (RBI.getRegBank(DstReg, MRI, TRI)->getID() != AArch64::FPRRegBankID) { in selectExtractElt()
[all …]
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| /external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64RegisterBankInfo.cpp | 56 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
248 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
325 getCopyMapping(AArch64::FPRRegBankID, AArch64::FPRRegBankID, Size), in getInstrAlternativeMappings()
330 getCopyMapping(AArch64::FPRRegBankID, AArch64::GPRRegBankID, Size), in getInstrAlternativeMappings()
335 getCopyMapping(AArch64::GPRRegBankID, AArch64::FPRRegBankID, Size), in getInstrAlternativeMappings()
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| D | AArch64InstructionSelector.cpp | 471 if (RB.getID() == AArch64::FPRRegBankID) { in getRegClassForTypeOnBank()
502 if (RegBankID == AArch64::FPRRegBankID) { in getMinClassForRegBank()
555 case AArch64::FPRRegBankID: in getMinSizeForRegBank()
665 case AArch64::FPRRegBankID: in selectBinaryOp()
722 case AArch64::FPRRegBankID: in selectLoadStoreUIOp()
764 assert((DstSize <= 64 || DstBank.getID() == AArch64::FPRRegBankID) && in isValidCopy()
1769 getRegClassForTypeOnBank(Ty, RBI.getRegBank(AArch64::FPRRegBankID), RBI); in selectVectorAshrLshr()
1968 MRI.setRegBank(PtrToInt.getReg(0), RBI.getRegBank(AArch64::FPRRegBankID)); in convertPtrAddToAdd()
2305 if (RB.getID() != AArch64::FPRRegBankID) { in select()
2409 assert(SrcRB.getID() == AArch64::FPRRegBankID && in select()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMRegisterBankInfo.cpp | 60 checkPartMapping(PartMappings[PMI_SPR - PMI_Min], 0, 32, FPRRegBankID) && in checkPartialMappings()
63 checkPartMapping(PartMappings[PMI_DPR - PMI_Min], 0, 64, FPRRegBankID) && in checkPartialMappings()
203 return getRegBank(ARM::FPRRegBankID); in getRegBankFromRegClass()
475 (Mapping.RegBank->getID() != ARM::FPRRegBankID || in getInstrMapping()
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| D | ARMInstructionSelector.cpp | 196 RegBank->getID() == ARM::FPRRegBankID) && in guessRegClass()
199 if (RegBank->getID() == ARM::FPRRegBankID) { in guessRegClass()
245 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues()
287 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectUnmergeValues()
376 if (RegBank == ARM::FPRRegBankID) { in selectLoadStoreOpCode()
924 if (SrcRegBank.getID() == ARM::FPRRegBankID) { in select()
1058 Opcodes.MOVCCi, ARM::FPRRegBankID, Size); in select()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMRegisterBankInfo.cpp | 60 checkPartMapping(PartMappings[PMI_SPR - PMI_Min], 0, 32, FPRRegBankID) && in checkPartialMappings()
63 checkPartMapping(PartMappings[PMI_DPR - PMI_Min], 0, 64, FPRRegBankID) && in checkPartialMappings()
205 return getRegBank(ARM::FPRRegBankID); in getRegBankFromRegClass()
477 (Mapping.RegBank->getID() != ARM::FPRRegBankID || in getInstrMapping()
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| D | ARMInstructionSelector.cpp | 194 RegBank->getID() == ARM::FPRRegBankID) && in guessRegClass()
197 if (RegBank->getID() == ARM::FPRRegBankID) { in guessRegClass()
243 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues()
285 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectUnmergeValues()
374 if (RegBank == ARM::FPRRegBankID) { in selectLoadStoreOpCode()
922 if (SrcRegBank.getID() == ARM::FPRRegBankID) { in select()
1056 Opcodes.MOVCCi, ARM::FPRRegBankID, Size); in select()
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