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Searched refs:FP_EXTEND (Results 1 – 25 of 88) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h480 FP_EXTEND, enumerator
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DConstrainedOps.def43 INSTRUCTION(FPExt, 1, 0, experimental_constrained_fpext, FP_EXTEND)
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp84 { ISD::FP_EXTEND, MVT::v2f32, 2 }, in getCastInstrCost()
85 { ISD::FP_EXTEND, MVT::v4f32, 4 } in getCastInstrCost()
89 ISD == ISD::FP_EXTEND)) { in getCastInstrCost()
/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp640 case ISD::FP_EXTEND: in isNegatibleForFree()
716 case ISD::FP_EXTEND: in GetNegatedExpression()
1418 case ISD::FP_EXTEND: return visitFP_EXTEND(N); in visit()
7819 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
7823 DAG.getNode(ISD::FP_EXTEND, SL, VT, in visitFADDForFMACombine()
7825 DAG.getNode(ISD::FP_EXTEND, SL, VT, in visitFADDForFMACombine()
7831 if (N1.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
7835 DAG.getNode(ISD::FP_EXTEND, SL, VT, in visitFADDForFMACombine()
7837 DAG.getNode(ISD::FP_EXTEND, SL, VT, in visitFADDForFMACombine()
7873 DAG.getNode(ISD::FP_EXTEND, SL, VT, U), in visitFADDForFMACombine()
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DLegalizeFloatTypes.cpp94 case ISD::FP_EXTEND: R = SoftenFloatRes_FP_EXTEND(N); break; in SoftenFloatResult()
460 Op = DAG.getNode(ISD::FP_EXTEND, SDLoc(N), MVT::f32, Op); in SoftenFloatRes_FP_EXTEND()
658 auto ExtendNode = DAG.getNode(ISD::FP_EXTEND, dl, VT, NewL); in SoftenFloatRes_LOAD()
756 case ISD::FP_EXTEND: Res = SoftenFloatOp_FP_EXTEND(N); break; in SoftenFloatOperand()
1034 case ISD::FP_EXTEND: ExpandFloatRes_FP_EXTEND(N, Lo, Hi); break; in ExpandFloatResult()
1271 Hi = DAG.getNode(ISD::FP_EXTEND, dl, NVT, N->getOperand(0)); in ExpandFloatRes_FP_EXTEND()
1749 case ISD::FP_EXTEND: R = PromoteFloatOp_FP_EXTEND(N, OpNo); break; in PromoteFloatOperand()
1800 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Op); in PromoteFloatOp_FP_EXTEND()
2131 ISD::FP_EXTEND, DL, NVT, in PromoteFloatRes_XINT_TO_FP()
DLegalizeDAG.cpp2325 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); in ExpandLegalINT_TO_FP()
2890 case ISD::FP_EXTEND: in ExpandNode()
3176 DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res)); in ExpandNode()
4122 ExtOp = ISD::FP_EXTEND; in PromoteNode()
4153 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode()
4166 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode()
4187 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
4188 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1)); in PromoteNode()
4196 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
4197 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1)); in PromoteNode()
[all …]
DLegalizeVectorOps.cpp325 case ISD::FP_EXTEND: in LegalizeOp()
416 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j)); in Promote()
DSelectionDAGDumper.cpp252 case ISD::FP_EXTEND: return "fp_extend"; in getOperationName()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h610 FP_EXTEND, enumerator
/external/llvm-project/llvm/include/llvm/IR/
DConstrainedOps.def57 DAG_INSTRUCTION(FPExt, 1, 0, experimental_constrained_fpext, FP_EXTEND)
/external/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h760 FP_EXTEND, enumerator
/external/llvm-project/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp478 {ISD::FP_EXTEND, MVT::v4f32, MVT::v4f16, 1}, in getCastInstrCost()
479 {ISD::FP_EXTEND, MVT::v8f32, MVT::v8f16, 3}, in getCastInstrCost()
547 (ISD == ISD::FP_EXTEND && SrcTy.getScalarType() == MVT::f32 && in getCastInstrCost()
552 {ISD::FP_EXTEND, MVT::v2f32, 2}, in getCastInstrCost()
553 {ISD::FP_EXTEND, MVT::v4f32, 4}}; in getCastInstrCost()
739 if (ISD == ISD::FP_ROUND || ISD == ISD::FP_EXTEND) { in getCastInstrCost()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp102 case ISD::FP_EXTEND: R = SoftenFloatRes_FP_EXTEND(N); break; in SoftenFloatResult()
488 Op = DAG.getNode(ISD::FP_EXTEND, SDLoc(N), MVT::f32, Op); in SoftenFloatRes_FP_EXTEND()
677 auto ExtendNode = DAG.getNode(ISD::FP_EXTEND, dl, VT, NewL); in SoftenFloatRes_LOAD()
1164 case ISD::FP_EXTEND: ExpandFloatRes_FP_EXTEND(N, Lo, Hi); break; in ExpandFloatResult()
1436 Hi = DAG.getNode(ISD::FP_EXTEND, dl, NVT, N->getOperand(0)); in ExpandFloatRes_FP_EXTEND()
1974 case ISD::FP_EXTEND: R = PromoteFloatOp_FP_EXTEND(N, OpNo); break; in PromoteFloatOperand()
2026 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Op); in PromoteFloatOp_FP_EXTEND()
2375 ISD::FP_EXTEND, DL, NVT, in PromoteFloatRes_XINT_TO_FP()
DDAGCombiner.cpp1584 case ISD::FP_EXTEND: return visitFP_EXTEND(N); in visit()
9427 CastOpcode == ISD::TRUNCATE || CastOpcode == ISD::FP_EXTEND || in matchVSelectOpSizesWithSetCC()
11579 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
11585 DAG.getNode(ISD::FP_EXTEND, SL, VT, in visitFADDForFMACombine()
11587 DAG.getNode(ISD::FP_EXTEND, SL, VT, in visitFADDForFMACombine()
11594 if (N1.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
11600 DAG.getNode(ISD::FP_EXTEND, SL, VT, in visitFADDForFMACombine()
11602 DAG.getNode(ISD::FP_EXTEND, SL, VT, in visitFADDForFMACombine()
11643 DAG.getNode(ISD::FP_EXTEND, SL, VT, U), in visitFADDForFMACombine()
11644 DAG.getNode(ISD::FP_EXTEND, SL, VT, V), in visitFADDForFMACombine()
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DLegalizeDAG.cpp2921 case ISD::FP_EXTEND: in ExpandNode()
3219 DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res)); in ExpandNode()
4388 ExtOp = ISD::FP_EXTEND; in PromoteNode()
4420 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode()
4433 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode()
4454 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
4455 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1)); in PromoteNode()
4477 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
4478 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1)); in PromoteNode()
4479 Tmp3 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(2)); in PromoteNode()
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DLegalizeVectorOps.cpp436 case ISD::FP_EXTEND: in LegalizeOp()
574 case ISD::FP_EXTEND: in Promote()
599 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(j)); in Promote()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp162 { ISD::FP_EXTEND, MVT::v2f32, 2 }, in getCastInstrCost()
163 { ISD::FP_EXTEND, MVT::v4f32, 4 } in getCastInstrCost()
167 ISD == ISD::FP_EXTEND)) { in getCastInstrCost()
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp102 case ISD::FP_EXTEND: R = SoftenFloatRes_FP_EXTEND(N); break; in SoftenFloatResult()
507 Op = DAG.getNode(ISD::FP_EXTEND, SDLoc(N), MVT::f32, Op); in SoftenFloatRes_FP_EXTEND()
705 auto ExtendNode = DAG.getNode(ISD::FP_EXTEND, dl, VT, NewL); in SoftenFloatRes_LOAD()
1202 case ISD::FP_EXTEND: ExpandFloatRes_FP_EXTEND(N, Lo, Hi); break; in ExpandFloatResult()
1479 Hi = DAG.getNode(ISD::FP_EXTEND, dl, NVT, N->getOperand(0)); in ExpandFloatRes_FP_EXTEND()
2080 case ISD::FP_EXTEND: R = PromoteFloatOp_FP_EXTEND(N, OpNo); break; in PromoteFloatOperand()
2132 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Op); in PromoteFloatOp_FP_EXTEND()
2490 ISD::FP_EXTEND, DL, NVT, in PromoteFloatRes_XINT_TO_FP()
2867 case ISD::FP_EXTEND: Res = SoftPromoteHalfOp_FP_EXTEND(N); break; in SoftPromoteHalfOperand()
DDAGCombiner.cpp1706 case ISD::FP_EXTEND: return visitFP_EXTEND(N); in visit()
10323 CastOpcode == ISD::TRUNCATE || CastOpcode == ISD::FP_EXTEND || in matchVSelectOpSizesWithSetCC()
12604 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
12610 DAG.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(0)), in visitFADDForFMACombine()
12611 DAG.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(1)), in visitFADDForFMACombine()
12618 if (N1.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
12624 DAG.getNode(ISD::FP_EXTEND, SL, VT, N10.getOperand(0)), in visitFADDForFMACombine()
12625 DAG.getNode(ISD::FP_EXTEND, SL, VT, N10.getOperand(1)), in visitFADDForFMACombine()
12638 DAG.getNode(ISD::FP_EXTEND, SL, VT, U), in visitFADDForFMACombine()
12639 DAG.getNode(ISD::FP_EXTEND, SL, VT, V), in visitFADDForFMACombine()
[all …]
DLegalizeDAG.cpp3062 case ISD::FP_EXTEND: in ExpandNode()
3353 DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res)); in ExpandNode()
4597 ExtOp = ISD::FP_EXTEND; in PromoteNode()
4631 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode()
4658 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode()
4679 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
4680 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1)); in PromoteNode()
4702 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
4703 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1)); in PromoteNode()
4704 Tmp3 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(2)); in PromoteNode()
[all …]
DLegalizeVectorOps.cpp433 case ISD::FP_EXTEND: in LegalizeOp()
580 case ISD::FP_EXTEND: in Promote()
605 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(j)); in Promote()
DLegalizeVectorTypes.cpp93 case ISD::FP_EXTEND: in ScalarizeVectorResult()
613 case ISD::FP_EXTEND: in ScalarizeVectorOperand()
710 ? DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Res) in ScalarizeVecOp_EXTRACT_VECTOR_ELT()
811 SDValue Res = DAG.getNode(ISD::FP_EXTEND, SDLoc(N), in ScalarizeVecOp_FP_EXTEND()
944 case ISD::FP_EXTEND: in SplitVectorResult()
2103 case ISD::FP_EXTEND: in SplitVectorOperand()
2950 case ISD::FP_EXTEND: in WidenVectorResult()
4373 case ISD::FP_EXTEND: in WidenVectorOperand()
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp554 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, in getCastInstrCost()
555 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, in getCastInstrCost()
641 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, in getCastInstrCost()
719 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, in getCastInstrCost()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp163 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); in AArch64TargetLowering()
303 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote); in AArch64TargetLowering()
309 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
369 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand); in AArch64TargetLowering()
547 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand); in AArch64TargetLowering()
1212 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS); in emitComparison()
1213 RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS); in emitComparison()
1304 LHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, LHS); in emitConditionalComparison()
1305 RHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, RHS); in emitConditionalComparison()
1930 DAG.getNode(ISD::FP_EXTEND, dl, NewVT, Op.getOperand(0))); in LowerVectorFP_TO_INT()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp280 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); in AArch64TargetLowering()
502 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand); in AArch64TargetLowering()
729 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand); in AArch64TargetLowering()
1715 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS); in emitComparison()
1716 RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS); in emitComparison()
1816 LHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, LHS); in emitConditionalComparison()
1817 RHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, RHS); in emitConditionalComparison()
2566 DAG.getNode(ISD::FP_EXTEND, dl, NewVT, Op.getOperand(0))); in LowerVectorFP_TO_INT()
2582 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0)); in LowerVectorFP_TO_INT()
2604 DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, SrcVal)); in LowerFP_TO_INT()
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