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Searched refs:FP_TO_FP16 (Results 1 – 25 of 50) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h518 FP16_TO_FP, FP_TO_FP16, enumerator
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h635 FP16_TO_FP, FP_TO_FP16, enumerator
/external/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h786 FP_TO_FP16, enumerator
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp815 case ISD::FP_TO_FP16: // Same as FP_ROUND for softening purposes in SoftenFloatOperand()
862 assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16 || in SoftenFloatOp_FP_ROUND()
869 EVT FloatRVT = N->getOpcode() == ISD::FP_TO_FP16 ? MVT::f16 : RVT; in SoftenFloatOp_FP_ROUND()
2047 return ISD::FP_TO_FP16; in GetPromotionOpcode()
2197 case ISD::FP_TO_FP16: in PromoteFloatResult()
2719 return DAG.getNode(ISD::FP_TO_FP16, dl, MVT::i16, Res); in SoftPromoteHalfRes_FMAD()
2733 return DAG.getNode(ISD::FP_TO_FP16, dl, MVT::i16, Res); in SoftPromoteHalfRes_FPOWI()
2745 return DAG.getNode(ISD::FP_TO_FP16, SDLoc(N), MVT::i16, N->getOperand(0)); in SoftPromoteHalfRes_FP_ROUND()
2786 return DAG.getNode(ISD::FP_TO_FP16, dl, MVT::i16, Res); in SoftPromoteHalfRes_XINT_TO_FP()
2804 return DAG.getNode(ISD::FP_TO_FP16, dl, MVT::i16, Res); in SoftPromoteHalfRes_UnaryOp()
[all …]
DSelectionDAGDumper.cpp355 case ISD::FP_TO_FP16: return "fp_to_fp16"; in getOperationName()
DLegalizeDAG.cpp1000 case ISD::FP_TO_FP16: in LegalizeOp()
3371 case ISD::FP_TO_FP16: in ExpandNode()
3377 TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) { in ExpandNode()
3383 DAG.getNode(ISD::FP_TO_FP16, dl, Node->getValueType(0), FloatVal)); in ExpandNode()
4324 case ISD::FP_TO_FP16: { in ConvertNodeToLibcall()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp503 return DAG.getNode(ISD::FP_TO_FP16, SDLoc(N), NVT, Op); in SoftenFloatRes_FP_ROUND()
615 return DAG.getNode(ISD::FP_TO_FP16, SDLoc(N), NVT, N->getOperand(0)); in SoftenFloatRes_FTRUNC()
757 case ISD::FP_TO_FP16: // Same as FP_ROUND for softening purposes in SoftenFloatOperand()
850 assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16); in SoftenFloatOp_FP_ROUND()
854 EVT FloatRVT = N->getOpcode() == ISD::FP_TO_FP16 ? MVT::f16 : RVT; in SoftenFloatOp_FP_ROUND()
1727 return ISD::FP_TO_FP16; in GetPromotionOpcode()
1858 case ISD::FP_TO_FP16: in PromoteFloatResult()
DSelectionDAGDumper.cpp261 case ISD::FP_TO_FP16: return "fp_to_fp16"; in getOperationName()
DLegalizeDAG.cpp963 case ISD::FP_TO_FP16: in LegalizeOp()
3179 case ISD::FP_TO_FP16: in ExpandNode()
3184 TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) { in ExpandNode()
3190 DAG.getNode(ISD::FP_TO_FP16, dl, Node->getValueType(0), FloatVal)); in ExpandNode()
3930 case ISD::FP_TO_FP16: { in ConvertNodeToLibcall()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.h470 FP_TO_FP16, enumerator
DAMDGPUInstrInfo.td134 def AMDGPUfp_to_f16 : SDNode<"AMDGPUISD::FP_TO_FP16" , SDTFPToIntOp>;
DAMDGPUISelLowering.cpp362 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Custom); in AMDGPUTargetLowering()
363 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Custom); in AMDGPUTargetLowering()
1256 case ISD::FP_TO_FP16: return LowerFP_TO_FP16(Op, DAG); in LowerOperation()
2614 return DAG.getNode(AMDGPUISD::FP_TO_FP16, DL, Op.getValueType(), N0); in LowerFP_TO_FP16()
4296 NODE_NAME_CASE(FP_TO_FP16) in getTargetNodeName()
4425 case AMDGPUISD::FP_TO_FP16: in computeKnownBitsForTargetNode()
4572 case AMDGPUISD::FP_TO_FP16: in ComputeNumSignBitsForTargetNode()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.h463 FP_TO_FP16, enumerator
DAMDGPUInstrInfo.td140 def AMDGPUfp_to_f16 : SDNode<"AMDGPUISD::FP_TO_FP16" , SDTFPToIntOp>;
DAMDGPUISelLowering.cpp302 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Custom); in AMDGPUTargetLowering()
303 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Custom); in AMDGPUTargetLowering()
1150 case ISD::FP_TO_FP16: return LowerFP_TO_FP16(Op, DAG); in LowerOperation()
2616 return DAG.getNode(AMDGPUISD::FP_TO_FP16, DL, Op.getValueType(), N0); in LowerFP_TO_FP16()
4320 NODE_NAME_CASE(FP_TO_FP16) in getTargetNodeName()
4454 case AMDGPUISD::FP_TO_FP16: in computeKnownBitsForTargetNode()
4602 case AMDGPUISD::FP_TO_FP16: in ComputeNumSignBitsForTargetNode()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp777 case ISD::FP_TO_FP16: // Same as FP_ROUND for softening purposes in SoftenFloatOperand()
824 assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16 || in SoftenFloatOp_FP_ROUND()
831 EVT FloatRVT = N->getOpcode() == ISD::FP_TO_FP16 ? MVT::f16 : RVT; in SoftenFloatOp_FP_ROUND()
1941 return ISD::FP_TO_FP16; in GetPromotionOpcode()
2091 case ISD::FP_TO_FP16: in PromoteFloatResult()
DSelectionDAGDumper.cpp344 case ISD::FP_TO_FP16: return "fp_to_fp16"; in getOperationName()
DLegalizeDAG.cpp1001 case ISD::FP_TO_FP16: in LegalizeOp()
3222 case ISD::FP_TO_FP16: in ExpandNode()
3228 TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) { in ExpandNode()
3234 DAG.getNode(ISD::FP_TO_FP16, dl, Node->getValueType(0), FloatVal)); in ExpandNode()
4135 case ISD::FP_TO_FP16: { in ConvertNodeToLibcall()
/external/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h1484 ISD::FP_TO_FP16, 0),
1486 ISD::FP_TO_FP16, 0),
1488 ISD::FP_TO_FP16, 0),
DX86InstrFragmentsSIMD.td560 def X86cvtps2ph : SDNode<"ISD::FP_TO_FP16",
/external/llvm-project/llvm/lib/Target/VE/
DVEISelLowering.cpp208 setOperationAction(ISD::FP_TO_FP16, FPVT, Expand); in initSPUActions()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp106 setOperationAction(ISD::FP_TO_FP16, T, Expand); in WebAssemblyTargetLowering()
/external/llvm-project/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp1523 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in SparcTargetLowering()
1525 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in SparcTargetLowering()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td464 def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>;
/external/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp106 setOperationAction(ISD::FP_TO_FP16, T, Expand); in WebAssemblyTargetLowering()

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