| /external/python/cpython2/Lib/plat-sunos5/ |
| D | IN.py | 137 FSCALE = (1<<FSHIFT) variable
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| D | STROPTS.py | 134 FSCALE = (1<<FSHIFT) variable
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ScheduleZnver2.td | 980 // FSCALE.
981 def : InstRW<[WriteMicrocoded], (instrs FSCALE)>;
|
| D | X86ScheduleZnver1.td | 980 // FSCALE.
981 def : InstRW<[WriteMicrocoded], (instrs FSCALE)>;
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| D | X86ScheduleAtom.td | 806 def : InstRW<[AtomWrite01_77], (instrs FSCALE)>;
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| D | X86SchedHaswell.td | 802 // FSCALE.
807 def : InstRW<[HWWriteFSCALE], (instrs FSCALE)>;
|
| D | X86InstrFPStack.td | 750 def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", []>;
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ScheduleZnver2.td | 992 // FSCALE.
993 def : InstRW<[WriteMicrocoded], (instrs FSCALE)>;
|
| D | X86ScheduleZnver1.td | 983 // FSCALE.
984 def : InstRW<[WriteMicrocoded], (instrs FSCALE)>;
|
| D | X86ScheduleAtom.td | 809 def : InstRW<[AtomWrite01_77], (instrs FSCALE)>;
|
| D | X86SchedHaswell.td | 805 // FSCALE.
810 def : InstRW<[HWWriteFSCALE], (instrs FSCALE)>;
|
| D | X86InstrFPStack.td | 746 def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", []>;
|
| /external/llvm/lib/Target/X86/ |
| D | X86SchedHaswell.td | 1243 // FSCALE.
1248 def : InstRW<[WriteFSCALE], (instregex "FSCALE")>;
|
| D | X86InstrFPStack.td | 663 def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", [], IIC_FSCALE>;
|
| /external/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 764 #define FSCALE CHOICE(fscale, fscale, fscale) macro
1477 #define FSCALE fscale macro
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenSubtargetInfo.inc | 6380 {DBGFIELD("FSCALE") 1, false, false, 63, 1, 47, 1, 0, 0}, // #691
7757 {DBGFIELD("FSCALE") 1, false, false, 96, 2, 2, 1, 0, 0}, // #691
9134 {DBGFIELD("FSCALE") 1, false, false, 714, 2, 2, 1, 0, 0}, // #691
10511 {DBGFIELD("FSCALE") 1, false, false, 1, 1, 2, 1, 0, 0}, // #691
11888 {DBGFIELD("FSCALE") 1, false, false, 714, 2, 2, 1, 0, 0}, // #691
13265 {DBGFIELD("FSCALE") 1, false, false, 709, 2, 2, 1, 0, 0}, // #691
14642 {DBGFIELD("FSCALE") 50, false, false, 0, 0, 83, 1, 0, 0}, // #691
16019 {DBGFIELD("FSCALE") 1, false, false, 3805, 2, 2, 1, 0, 0}, // #691
17396 {DBGFIELD("FSCALE") 1, false, false, 714, 2, 2, 1, 0, 0}, // #691
18773 {DBGFIELD("FSCALE") 1, false, false, 0, 0, 2, 1, 0, 0}, // #691
[all …]
|
| D | X86GenAsmWriter.inc | 2675 15544U, // FSCALE
17926 0U, // FSCALE
33177 0U, // FSCALE
|
| D | X86GenAsmWriter1.inc | 2384 12314U, // FSCALE
17635 0U, // FSCALE
|
| D | X86GenDisassemblerTables.inc | 11399 /* FSCALE */
77302 0x3f0, /* FSCALE */
|
| D | X86GenAsmMatcher.inc | 8754 { 2802 /* fscale */, X86::FSCALE, Convert_NoOperands, AMFBS_None, { }, },
23326 { 2802 /* fscale */, X86::FSCALE, Convert_NoOperands, AMFBS_None, { }, },
|
| D | X86GenInstrInfo.inc | 1023 FSCALE = 1008,
15968 FSCALE = 691,
18708 …), 0x364000007dULL, ImplicitList17, ImplicitList12, nullptr, -1 ,nullptr }, // Inst #1008 = FSCALE
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | sve-intrinsics-fp-arith.ll | 1281 ; FSCALE
|
| /external/capstone/arch/X86/ |
| D | X86GenAsmWriter1.inc | 823 10313U, // FSCALE
9680 0U, // FSCALE
|
| D | X86GenAsmWriter.inc | 823 12904U, // FSCALE
9680 0U, // FSCALE
|
| D | X86GenDisassemblerTables.inc | 12951 /* FSCALE */
62292 0x326, /* FSCALE */
|