| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 471 SHL, SRA, SRL, ROTL, ROTR, FSHL, FSHR, enumerator
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 611 FSHL, enumerator
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 2329 { ISD::FSHL, MVT::i64, 4 } in getIntrinsicInstrCost()
2338 { ISD::FSHL, MVT::i32, 4 }, in getIntrinsicInstrCost()
2339 { ISD::FSHL, MVT::i16, 4 }, in getIntrinsicInstrCost()
2340 { ISD::FSHL, MVT::i8, 4 } in getIntrinsicInstrCost()
2348 ISD = ISD::FSHL; in getIntrinsicInstrCost()
2354 ISD = ISD::FSHL; in getIntrinsicInstrCost()
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 384 case ISD::FSHL: in LegalizeOp()
794 case ISD::FSHL: in Expand()
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| D | SelectionDAGDumper.cpp | 250 case ISD::FSHL: return "fshl"; in getOperationName()
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| D | LegalizeVectorTypes.cpp | 154 case ISD::FSHL: in ScalarizeVectorResult()
1007 case ISD::FSHL: in SplitVectorResult()
3009 case ISD::FSHL: in WidenVectorResult()
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| D | TargetLowering.cpp | 1673 case ISD::FSHL: in SimplifyDemandedBits()
1678 bool IsFSHL = (Op.getOpcode() == ISD::FSHL); in SimplifyDemandedBits()
6242 bool IsFSHL = Node->getOpcode() == ISD::FSHL; in expandFunnelShift()
6248 unsigned RevOpcode = IsFSHL ? ISD::FSHR : ISD::FSHL; in expandFunnelShift()
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| D | DAGCombiner.cpp | 1664 case ISD::FSHL: in visit()
6696 if (PosOpcode == ISD::FSHL && isPowerOf2_32(EltBits)) { in MatchFunnelPosNeg()
6709 TLI.isOperationLegalOrCustom(ISD::FSHL, VT)) { in MatchFunnelPosNeg()
6710 return DAG.getNode(ISD::FSHL, DL, VT, N0, N1.getOperand(0), Pos); in MatchFunnelPosNeg()
6749 bool HasFSHL = hasOperation(ISD::FSHL, VT); in MatchRotate()
6836 Res = DAG.getNode(HasFSHL ? ISD::FSHL : ISD::FSHR, DL, VT, LHSShiftArg, in MatchRotate()
6897 LExtOp0, RExtOp0, ISD::FSHL, ISD::FSHR, DL); in MatchRotate()
6903 RExtOp0, LExtOp0, ISD::FSHR, ISD::FSHL, DL); in MatchRotate()
8773 bool IsFSHL = N->getOpcode() == ISD::FSHL; in visitFunnelShift()
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| D | LegalizeDAG.cpp | 1218 case ISD::FSHL: in LegalizeOp()
3533 case ISD::FSHL: in ExpandNode()
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| D | LegalizeIntegerTypes.cpp | 220 case ISD::FSHL: in PromoteIntegerResult()
2171 case ISD::FSHL: in ExpandIntegerResult()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 246 case ISD::FSHL: return "fshl"; in getOperationName()
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| D | LegalizeVectorOps.cpp | 388 case ISD::FSHL: in LegalizeOp()
913 case ISD::FSHL: in Expand()
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| D | TargetLowering.cpp | 1539 case ISD::FSHL: in SimplifyDemandedBits()
1544 bool IsFSHL = (Op.getOpcode() == ISD::FSHL); in SimplifyDemandedBits()
5949 bool IsFSHL = Node->getOpcode() == ISD::FSHL; in expandFunnelShift()
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| D | LegalizeDAG.cpp | 1198 case ISD::FSHL: in LegalizeOp()
3400 case ISD::FSHL: in ExpandNode()
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| D | SelectionDAG.cpp | 2921 case ISD::FSHL: in computeKnownBits()
2929 Known = computeKnownBits(Op.getOperand(Opcode == ISD::FSHL ? 0 : 1), in computeKnownBits()
2938 if (Opcode == ISD::FSHL) { in computeKnownBits()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 2950 { ISD::FSHL, MVT::i64, 4 } in getIntrinsicInstrCost()
2959 { ISD::FSHL, MVT::i32, 4 }, in getIntrinsicInstrCost()
2960 { ISD::FSHL, MVT::i16, 4 }, in getIntrinsicInstrCost()
2961 { ISD::FSHL, MVT::i8, 4 } in getIntrinsicInstrCost()
2972 ISD = ISD::FSHL; in getIntrinsicInstrCost()
2978 ISD = ISD::FSHL; in getIntrinsicInstrCost()
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| D | X86ISelLowering.h | 38 FSHL, enumerator
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| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 237 setOperationAction(ISD::FSHL, XLenVT, Legal); in RISCVTargetLowering()
241 setOperationAction(ISD::FSHL, MVT::i32, Custom); in RISCVTargetLowering()
1213 case ISD::FSHL: in ReplaceNodeResults()
1228 N->getOpcode() == ISD::FSHL ? RISCVISD::FSLW : RISCVISD::FSRW; in ReplaceNodeResults()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 651 setOperationAction(ISD::FSHL, VT, Expand); in initActions()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1422 setOperationAction(ISD::FSHL, MVT::i32, Legal); in HexagonTargetLowering()
1423 setOperationAction(ISD::FSHL, MVT::i64, Legal); in HexagonTargetLowering()
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1555 setOperationAction(ISD::FSHL, MVT::i32, Legal); in HexagonTargetLowering()
1556 setOperationAction(ISD::FSHL, MVT::i64, Legal); in HexagonTargetLowering()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 761 setOperationAction(ISD::FSHL, VT, Expand); in initActions()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 369 def fshl : SDNode<"ISD::FSHL" , SDTIntShiftDOp>;
|
| /external/llvm-project/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 372 def fshl : SDNode<"ISD::FSHL" , SDTIntShiftDOp>;
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 685 setOperationAction(ISD::FSHL, MVT::i64, Custom); in PPCTargetLowering()
688 setOperationAction(ISD::FSHL, MVT::i32, Custom); in PPCTargetLowering()
9118 bool IsFSHL = Op.getOpcode() == ISD::FSHL; in LowerFunnelShift()
11057 case ISD::FSHL: return LowerFunnelShift(Op, DAG); in LowerOperation()
11153 case ISD::FSHL: in ReplaceNodeResults()
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