| /external/one-true-awk/ |
| D | awk.h | 147 #define FSIN 9 macro
|
| D | lex.c | 79 { "sin", FSIN, BLTIN },
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 524 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator
|
| D | BasicTTIImpl.h | 745 ISDs.push_back(ISD::FSIN); in getIntrinsicInstrCost()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | ConstrainedOps.def | 80 FUNCTION(sin, 1, 1, experimental_constrained_sin, FSIN)
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 640 FNEG, FABS, FSQRT, FCBRT, FSIN, FCOS, FPOWI, FPOW, enumerator
|
| /external/llvm-project/llvm/include/llvm/IR/ |
| D | ConstrainedOps.def | 95 DAG_FUNCTION(sin, 1, 1, experimental_constrained_sin, FSIN)
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 797 FSIN, enumerator
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 159 case ISD::FSIN: return "fsin"; in getOperationName()
|
| D | LegalizeFloatTypes.cpp | 102 case ISD::FSIN: R = SoftenFloatRes_FSIN(N); break; in SoftenFloatResult()
1039 case ISD::FSIN: ExpandFloatRes_FSIN(N, Lo, Hi); break; in ExpandFloatResult()
1882 case ISD::FSIN: in PromoteFloatResult()
|
| D | LegalizeDAG.cpp | 2180 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN in useSinCos()
2181 ? ISD::FCOS : ISD::FSIN; in useSinCos()
3149 case ISD::FSIN: in ExpandNode()
3817 case ISD::FSIN: in ConvertNodeToLibcall()
4229 case ISD::FSIN: in PromoteNode()
|
| D | LegalizeVectorOps.cpp | 309 case ISD::FSIN: in LegalizeOp()
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 81 for (auto Op : {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOWI, ISD::FPOW, in WebAssemblyTargetLowering()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 196 case ISD::FSIN: return "fsin"; in getOperationName()
|
| D | LegalizeFloatTypes.cpp | 117 case ISD::FSIN: R = SoftenFloatRes_FSIN(N); break; in SoftenFloatResult()
1174 case ISD::FSIN: ExpandFloatRes_FSIN(N, Lo, Hi); break; in ExpandFloatResult()
2120 case ISD::FSIN: in PromoteFloatResult()
|
| D | LegalizeDAG.cpp | 2259 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN in useSinCos()
2260 ? ISD::FCOS : ISD::FSIN; in useSinCos()
3192 case ISD::FSIN: in ExpandNode()
3960 case ISD::FSIN: in ConvertNodeToLibcall()
4509 case ISD::FSIN: in PromoteNode()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 145 setOperationAction(ISD::FSIN, MVT::f32, Custom); in R600TargetLowering()
488 case ISD::FSIN: return LowerTrig(Op, DAG); in LowerOperation()
775 case ISD::FSIN: in LowerTrig()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 145 setOperationAction(ISD::FSIN, MVT::f32, Custom); in R600TargetLowering()
488 case ISD::FSIN: return LowerTrig(Op, DAG); in LowerOperation()
780 case ISD::FSIN: in LowerTrig()
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 198 case ISD::FSIN: return "fsin"; in getOperationName()
|
| D | LegalizeFloatTypes.cpp | 119 case ISD::FSIN: R = SoftenFloatRes_FSIN(N); break; in SoftenFloatResult()
1215 case ISD::FSIN: ExpandFloatRes_FSIN(N, Lo, Hi); break; in ExpandFloatResult()
2227 case ISD::FSIN: in PromoteFloatResult()
2592 case ISD::FSIN: in SoftPromoteHalfResult()
|
| D | LegalizeDAG.cpp | 2316 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN in useSinCos()
2317 ? ISD::FCOS : ISD::FSIN; in useSinCos()
3326 case ISD::FSIN: in ExpandNode()
4130 case ISD::FSIN: in ConvertNodeToLibcall()
4735 case ISD::FSIN: in PromoteNode()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 108 setOperationAction(ISD::FSIN, MVT::f32, Custom); in R600TargetLowering()
625 case ISD::FSIN: return LowerTrig(Op, DAG); in LowerOperation()
949 case ISD::FSIN: in LowerTrig()
|
| D | SIISelLowering.cpp | 216 setOperationAction(ISD::FSIN, MVT::f32, Custom); in SITargetLowering()
1241 case ISD::FSIN: in LowerOperation()
2375 case ISD::FSIN: in LowerTrig()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ScheduleAtom.td | 891 def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>;
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ScheduleAtom.td | 894 def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>;
|