/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
D | legalize-fsqrt.mir | 14 ; SI: [[FSQRT:%[0-9]+]]:_(s32) = G_FSQRT [[COPY]] 15 ; SI: $vgpr0 = COPY [[FSQRT]](s32) 18 ; VI: [[FSQRT:%[0-9]+]]:_(s32) = G_FSQRT [[COPY]] 19 ; VI: $vgpr0 = COPY [[FSQRT]](s32) 22 ; GFX9: [[FSQRT:%[0-9]+]]:_(s32) = G_FSQRT [[COPY]] 23 ; GFX9: $vgpr0 = COPY [[FSQRT]](s32) 37 ; SI: [[FSQRT:%[0-9]+]]:_(s64) = G_FSQRT [[COPY]] 38 ; SI: $vgpr0_vgpr1 = COPY [[FSQRT]](s64) 41 ; VI: [[FSQRT:%[0-9]+]]:_(s64) = G_FSQRT [[COPY]] 42 ; VI: $vgpr0_vgpr1 = COPY [[FSQRT]](s64) [all …]
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D | regbankselect-fsqrt.mir | 15 ; CHECK: [[FSQRT:%[0-9]+]]:vgpr(s32) = G_FSQRT [[COPY1]] 16 ; CHECK: $vgpr0 = COPY [[FSQRT]](s32) 31 ; CHECK: [[FSQRT:%[0-9]+]]:vgpr(s32) = G_FSQRT [[COPY]] 32 ; CHECK: $vgpr0 = COPY [[FSQRT]](s32)
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/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ |
D | fsqrt.mir | 21 ; FP32: [[FSQRT:%[0-9]+]]:_(s32) = G_FSQRT [[COPY]] 22 ; FP32: $f0 = COPY [[FSQRT]](s32) 27 ; FP64: [[FSQRT:%[0-9]+]]:_(s32) = G_FSQRT [[COPY]] 28 ; FP64: $f0 = COPY [[FSQRT]](s32) 47 ; FP32: [[FSQRT:%[0-9]+]]:_(s64) = G_FSQRT [[COPY]] 48 ; FP32: $d0 = COPY [[FSQRT]](s64) 53 ; FP64: [[FSQRT:%[0-9]+]]:_(s64) = G_FSQRT [[COPY]] 54 ; FP64: $d0 = COPY [[FSQRT]](s64)
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D | fsqrt_vec.mir | 22 ; P5600: [[FSQRT:%[0-9]+]]:_(<4 x s32>) = G_FSQRT [[LOAD]] 23 ; P5600: G_STORE [[FSQRT]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c) 46 ; P5600: [[FSQRT:%[0-9]+]]:_(<2 x s64>) = G_FSQRT [[LOAD]] 47 ; P5600: G_STORE [[FSQRT]](<2 x s64>), [[COPY1]](p0) :: (store 16 into %ir.c)
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D | fsqrt_vec_builtin.mir | 25 ; P5600: [[FSQRT:%[0-9]+]]:_(<4 x s32>) = G_FSQRT [[LOAD]] 26 ; P5600: G_STORE [[FSQRT]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c) 49 ; P5600: [[FSQRT:%[0-9]+]]:_(<2 x s64>) = G_FSQRT [[LOAD]] 50 ; P5600: G_STORE [[FSQRT]](<2 x s64>), [[COPY1]](p0) :: (store 16 into %ir.c)
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/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/ |
D | fsqrt.mir | 22 ; FP32: [[FSQRT:%[0-9]+]]:fprb(s32) = G_FSQRT [[COPY]] 23 ; FP32: $f0 = COPY [[FSQRT]](s32) 28 ; FP64: [[FSQRT:%[0-9]+]]:fprb(s32) = G_FSQRT [[COPY]] 29 ; FP64: $f0 = COPY [[FSQRT]](s32) 49 ; FP32: [[FSQRT:%[0-9]+]]:fprb(s64) = G_FSQRT [[COPY]] 50 ; FP32: $d0 = COPY [[FSQRT]](s64) 55 ; FP64: [[FSQRT:%[0-9]+]]:fprb(s64) = G_FSQRT [[COPY]] 56 ; FP64: $d0 = COPY [[FSQRT]](s64)
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D | fsqrt_vec.mir | 23 ; P5600: [[FSQRT:%[0-9]+]]:fprb(<4 x s32>) = G_FSQRT [[LOAD]] 24 ; P5600: G_STORE [[FSQRT]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c) 48 ; P5600: [[FSQRT:%[0-9]+]]:fprb(<2 x s64>) = G_FSQRT [[LOAD]] 49 ; P5600: G_STORE [[FSQRT]](<2 x s64>), [[COPY1]](p0) :: (store 16 into %ir.c)
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
D | X86TargetTransformInfo.cpp | 1997 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ in getIntrinsicInstrCost() 1998 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ in getIntrinsicInstrCost() 1999 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ in getIntrinsicInstrCost() 2000 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ in getIntrinsicInstrCost() 2001 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ in getIntrinsicInstrCost() 2002 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ in getIntrinsicInstrCost() 2034 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ in getIntrinsicInstrCost() 2035 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ in getIntrinsicInstrCost() 2036 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ in getIntrinsicInstrCost() 2037 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ in getIntrinsicInstrCost() [all …]
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/external/llvm-project/llvm/lib/Target/X86/ |
D | X86TargetTransformInfo.cpp | 2478 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ in getTypeBasedIntrinsicInstrCost() 2479 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ in getTypeBasedIntrinsicInstrCost() 2480 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ in getTypeBasedIntrinsicInstrCost() 2481 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ in getTypeBasedIntrinsicInstrCost() 2482 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ in getTypeBasedIntrinsicInstrCost() 2483 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ in getTypeBasedIntrinsicInstrCost() 2537 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ in getTypeBasedIntrinsicInstrCost() 2538 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ in getTypeBasedIntrinsicInstrCost() 2539 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ in getTypeBasedIntrinsicInstrCost() 2540 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ in getTypeBasedIntrinsicInstrCost() [all …]
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/external/one-true-awk/ |
D | awk.h | 140 #define FSQRT 2 macro
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D | lex.c | 82 { "sqrt", FSQRT, BLTIN },
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/external/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 524 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator
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D | BasicTTIImpl.h | 201 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT); in haveFastSqrt() 742 ISDs.push_back(ISD::FSQRT); in getIntrinsicInstrCost()
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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
D | ConstrainedOps.def | 81 FUNCTION(sqrt, 1, 1, experimental_constrained_sqrt, FSQRT)
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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 640 FNEG, FABS, FSQRT, FCBRT, FSIN, FCOS, FPOWI, FPOW, enumerator
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D | BasicTTIImpl.h | 397 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT); in haveFastSqrt() 1220 ISDs.push_back(ISD::FSQRT);
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/external/llvm-project/llvm/include/llvm/IR/ |
D | ConstrainedOps.def | 96 DAG_FUNCTION(sqrt, 1, 1, experimental_constrained_sqrt, FSQRT)
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/external/llvm-project/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 795 FSQRT, enumerator
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/external/llvm/lib/Target/X86/ |
D | X86IntrinsicsInfo.h | 265 X86_INTRINSIC_DATA(avx_sqrt_pd_256, INTR_TYPE_1OP, ISD::FSQRT, 0), 266 X86_INTRINSIC_DATA(avx_sqrt_ps_256, INTR_TYPE_1OP, ISD::FSQRT, 0), 1429 X86_INTRINSIC_DATA(avx512_mask_sqrt_pd_128, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0), 1430 X86_INTRINSIC_DATA(avx512_mask_sqrt_pd_256, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0), 1431 X86_INTRINSIC_DATA(avx512_mask_sqrt_pd_512, INTR_TYPE_1OP_MASK_RM, ISD::FSQRT, 1433 X86_INTRINSIC_DATA(avx512_mask_sqrt_ps_128, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0), 1434 X86_INTRINSIC_DATA(avx512_mask_sqrt_ps_256, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0), 1435 X86_INTRINSIC_DATA(avx512_mask_sqrt_ps_512, INTR_TYPE_1OP_MASK_RM, ISD::FSQRT, 1873 X86_INTRINSIC_DATA(sse_sqrt_ps, INTR_TYPE_1OP, ISD::FSQRT, 0), 1923 X86_INTRINSIC_DATA(sse2_sqrt_pd, INTR_TYPE_1OP, ISD::FSQRT, 0),
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/external/llvm/lib/Target/PowerPC/ |
D | PPCCTRLoops.cpp | 301 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; in mightUseCTR() 344 Opcode = ISD::FSQRT; break; in mightUseCTR()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
D | PPCTargetTransformInfo.cpp | 311 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; in mightUseCTR() 360 Opcode = ISD::FSQRT; break; in mightUseCTR()
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/external/llvm-project/llvm/lib/Target/PowerPC/ |
D | PPCTargetTransformInfo.cpp | 470 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; in mightUseCTR() 567 Opcode = ISD::FSQRT; break; in mightUseCTR()
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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/ |
D | PPCGenSubtargetInfo.inc | 3652 { 0, 0, 0, 0, 0 }, // 262 FSQRT 3971 { 0, 0, 0, 0, 0 }, // 262 FSQRT 4290 { 0, 0, 0, 0, 0 }, // 262 FSQRT 4609 { 0, 0, 0, 0, 0 }, // 262 FSQRT 4928 { 1, 164, 165, 0, 0 }, // 262 FSQRT 5247 { 1, 185, 186, 1018, 1021 }, // 262 FSQRT 5566 { 0, 0, 0, 0, 0 }, // 262 FSQRT 5885 { 0, 0, 0, 0, 0 }, // 262 FSQRT 6204 { 0, 0, 0, 0, 0 }, // 262 FSQRT 6523 { 1, 321, 323, 3059, 3062 }, // 262 FSQRT [all …]
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | SelectionDAGDumper.cpp | 158 case ISD::FSQRT: return "fsqrt"; in getOperationName()
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/external/llvm-project/llvm/lib/Target/AArch64/ |
D | AArch64SchedCyclone.td | 549 // FDIV,FSQRT 551 // TODO: Specialize FSQRT for longer latency.
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