| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeSPARC_common.c | 156 #define FSUBS (OPC1(0x2) | OPC3(0x34) | DOP(0x45)) macro
1217 …FAIL_IF(push_inst(compiler, SELECT_FOP(op, FSUBS, FSUBD) | FD(dst_r) | FS1(src1) | FS2(src2), MOVA… in sljit_emit_fop2()
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| D | sljitNativePPC_common.c | 183 #define FSUBS (HI(59) | LO(20)) macro
1848 FAIL_IF(push_inst(compiler, SELECT_FOP(op, FSUBS, FSUB) | FD(dst_r) | FA(src1) | FB(src2))); in sljit_emit_fop2()
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| /external/llvm/lib/Target/Sparc/ |
| D | LeonPasses.cpp | 860 case SP::FSUBS: in runOnMachineFunction()
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| D | SparcInstrInfo.td | 1217 def FSUBS : F3_3<2, 0b110100, 0b001000101,
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 215 FSUBS, enumerator
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| D | X86IntrinsicsInfo.h | 783 X86ISD::FSUBS, X86ISD::FSUBS_RND),
785 X86ISD::FSUBS, X86ISD::FSUBS_RND),
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| D | X86InstrFragmentsSIMD.td | 517 def X86fsubs : SDNode<"X86ISD::FSUBS", SDTFPBinOp>;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 783 X86ISD::FSUBS, X86ISD::FSUBS_RND),
785 X86ISD::FSUBS, X86ISD::FSUBS_RND),
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| D | X86ISelLowering.h | 208 FSUB_RND, FSUBS, FSUBS_RND, enumerator
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| D | X86InstrFragmentsSIMD.td | 508 def X86fsubs : SDNode<"X86ISD::FSUBS", SDTFPBinOp>;
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenMCCodeEmitter.inc | 999 UINT64_C(3959423016), // FSUBS
3408 case PPC::FSUBS:
7409 CEFBS_None, // FSUBS = 986
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| D | PPCGenFastISel.inc | 2262 return fastEmitInst_rr(PPC::FSUBS, &PPC::F4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
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| D | PPCGenInstrInfo.inc | 1001 FSUBS = 986,
3970 …, 4, 148, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #986 = FSUBS
12679 { PPC::FSUBS_rec, PPC::FSUBS },
12881 { PPC::FSUBS, PPC::FSUBS_rec },
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| D | PPCGenAsmWriter.inc | 2654 25495U, // FSUBS
4945 38U, // FSUBS
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| D | PPCGenDisassemblerTables.inc | 2396 /* 11168 */ MCD::OPC_Decode, 218, 7, 126, // Opcode: FSUBS
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| /external/capstone/arch/Sparc/ |
| D | SparcGenDisassemblerTables.inc | 614 /* 2361 */ MCD_OPC_Decode, 162, 2, 26, // Opcode: FSUBS
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| D | SparcGenAsmWriter.inc | 311 5630U, // FSUBS
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.td | 1225 def FSUBS : F3_3<2, 0b110100, 0b001000101,
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| /external/llvm-project/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.td | 1225 def FSUBS : F3_3<2, 0b110100, 0b001000101,
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| /external/llvm-project/llvm/lib/Target/VE/ |
| D | VEInstrInfo.td | 1346 defm FSUBS : RRFm<"fsub.s", 0x5C, F32, f32, fsub, simm7fp, mimmfp32>;
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| /external/capstone/arch/PowerPC/ |
| D | PPCGenAsmWriter.inc | 600 22553U, // FSUBS
2122 0U, // FSUBS
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| D | PPCGenDisassemblerTables.inc | 1593 /* 6575 */ MCD_OPC_Decode, 196, 4, 87, // Opcode: FSUBS
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 2617 defm FSUBS : AForm_2r<59, 20,
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 3026 defm FSUBS : AForm_2r<59, 20,
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 3239 defm FSUBS : AForm_2r<59, 20,
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