| /external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ |
| D | float_arithmetic_operations.mir | 61 ; FP32: [[FSUB_S:%[0-9]+]]:fgr32 = FSUB_S [[COPY]], [[COPY1]]
62 ; FP32: $f0 = COPY [[FSUB_S]]
68 ; FP64: [[FSUB_S:%[0-9]+]]:fgr32 = FSUB_S [[COPY]], [[COPY1]]
69 ; FP64: $f0 = COPY [[FSUB_S]]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfoF.td | 136 def FSUB_S : FPALUS_rr_frm<0b0000100, "fsub.s">,
138 def : FPALUSDynFrmAlias<FSUB_S, "fsub.s">;
306 def : PatFpr32Fpr32DynFrm<fsub, FSUB_S>;
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| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfoF.td | 135 def FSUB_S : FPALUS_rr_frm<0b0000100, "fsub.s">,
137 def : FPALUSDynFrmAlias<FSUB_S, "fsub.s">;
312 def : PatFpr32Fpr32DynFrm<fsub, FSUB_S>;
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrFPU.td | 477 def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsScheduleP5600.td | 452 FSUB_D32, FSUB_D64, FSUB_S)>;
|
| D | MipsInstrFPU.td | 645 def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
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| D | MipsScheduleGeneric.td | 813 FSUB_S, FSUB_D32, FSUB_D64)>;
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsScheduleP5600.td | 453 FMUL_PS64, FMUL_S, FSUB_D32, FSUB_D64, FSUB_PS64, FSUB_S)>;
|
| D | MipsInstrFPU.td | 678 def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
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| D | MipsScheduleGeneric.td | 813 FSUB_S, FSUB_D32, FSUB_D64)>;
|
| /external/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 780 #define FSUB_S(a) CHOICE(fsubs a, fsubs a, fsubs a) macro
1493 #define FSUB_S(a) fsub S_(a) macro
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 888 {DBGFIELD("FSUB_S") 1, false, false, 14, 2, 4, 1, 0, 0}, // #628
2572 {DBGFIELD("FSUB_S") 1, false, false, 57, 2, 4, 1, 0, 0}, // #628
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| D | MipsGenMCCodeEmitter.inc | 1623 UINT64_C(1174405121), // FSUB_S
3520 case Mips::FSUB_S:
11085 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FSUB_S = 1610
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| D | MipsGenAsmWriter.inc | 2851 268458807U, // FSUB_S
5605 0U, // FSUB_S
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| D | MipsGenInstrInfo.inc | 1625 FSUB_S = 1610,
3408 FSUB_S = 628,
6471 …, 3, 1, 4, 628, 0, 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1610 = FSUB_S
16802 { Mips::FSUB_S, Mips::FSUB_S, Mips::FSUB_S_MM },
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| D | MipsGenFastISel.inc | 1637 return fastEmitInst_rr(Mips::FSUB_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
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| D | MipsGenDisassemblerTables.inc | 3363 /* 2637 */ MCD::OPC_Decode, 202, 12, 207, 1, // Opcode: FSUB_S
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| D | MipsGenAsmMatcher.inc | 7842 …{ 8850 /* sub.s */, Mips::FSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_H…
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| D | MipsGenGlobalISel.inc | 21905 …// (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S:{ *:[f32] …
21906 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_S,
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| D | MipsGenDAGISel.inc | 27020 /* 51119*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSUB_S), 0,
27023 … // Dst: (FSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
|
| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 833 134240554U, // FSUB_S
2622 0U, // FSUB_S
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| D | MipsGenDisassemblerTables.inc | 1043 /* 1817 */ MCD_OPC_Decode, 176, 6, 93, // Opcode: FSUB_S
|