| /external/vixl/examples/aarch64/ |
| D | neon-matrix-multiply.cc | 54 __ Fmul(v_out, v4.V4S(), v_in, 0); // e.g. (v0.V4S(), v4.V4S(), v8.S(), 0). in GenerateMultiplyColumn() local
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| /external/vixl/test/aarch64/ |
| D | test-assembler-fp-aarch64.cc | 634 __ Fmul(s0, s17, s18); in TEST() local
635 __ Fmul(s1, s18, s19); in TEST() local
636 __ Fmul(s2, s14, s14); in TEST() local
637 __ Fmul(s3, s15, s20); in TEST() local
638 __ Fmul(s4, s16, s20); in TEST() local
639 __ Fmul(s5, s15, s19); in TEST() local
640 __ Fmul(s6, s19, s16); in TEST() local
642 __ Fmul(d7, d30, d31); in TEST() local
643 __ Fmul(d8, d29, d31); in TEST() local
644 __ Fmul(d9, d26, d26); in TEST() local
[all …]
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| D | test-disasm-neon-aarch64.cc | 1849 COMPARE_MACRO(Fmul(v22.V8H(), v23.V8H(), v24.V8H()), in TEST()
1851 COMPARE_MACRO(Fmul(v25.V4H(), v26.V4H(), v27.V4H()), in TEST()
1949 COMPARE_MACRO(Fmul(v6.M, v7.M, v8.M), "fmul v6." S ", v7." S ", v8." S); in TEST()
2435 COMPARE_MACRO(Fmul(v0.V4H(), v1.V4H(), v2.H(), 0), in TEST()
2437 COMPARE_MACRO(Fmul(v2.V8H(), v3.V8H(), v15.H(), 3), in TEST()
2439 COMPARE_MACRO(Fmul(v0.V2S(), v1.V2S(), v2.S(), 0), in TEST()
2441 COMPARE_MACRO(Fmul(v2.V4S(), v3.V4S(), v15.S(), 3), in TEST()
2443 COMPARE_MACRO(Fmul(v0.V2D(), v1.V2D(), v2.D(), 0), in TEST()
2445 COMPARE_MACRO(Fmul(d0, d1, v2.D(), 0), "fmul d0, d1, v2.d[0]"); in TEST()
2446 COMPARE_MACRO(Fmul(s0, s1, v2.S(), 0), "fmul s0, s1, v2.s[0]"); in TEST()
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| D | test-assembler-sve-aarch64.cc | 12289 ArithFn fn = &MacroAssembler::Fmul; in TEST_SVE()
14877 __ Fmul(z2.VnH(), z1.VnH(), z0.VnH(), 0); in TEST_SVE() local
14878 __ Fmul(z3.VnH(), z1.VnH(), z0.VnH(), 1); in TEST_SVE() local
14879 __ Fmul(z4.VnH(), z1.VnH(), z0.VnH(), 4); in TEST_SVE() local
14880 __ Fmul(z5.VnH(), z1.VnH(), z0.VnH(), 7); in TEST_SVE() local
14882 __ Fmul(z6.VnS(), z1.VnS(), z0.VnS(), 0); in TEST_SVE() local
14883 __ Fmul(z7.VnS(), z1.VnS(), z0.VnS(), 1); in TEST_SVE() local
14884 __ Fmul(z8.VnS(), z1.VnS(), z0.VnS(), 2); in TEST_SVE() local
14885 __ Fmul(z9.VnS(), z1.VnS(), z0.VnS(), 3); in TEST_SVE() local
14887 __ Fmul(z10.VnD(), z1.VnD(), z0.VnD(), 0); in TEST_SVE() local
[all …]
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| D | test-assembler-neon-aarch64.cc | 3773 __ Fmul(v6.V4H(), v1.V4H(), v0.V4H()); in TEST() local
3774 __ Fmul(v7.V8H(), v3.V8H(), v2.V8H()); in TEST() local
3775 __ Fmul(v8.V4H(), v4.V4H(), v3.V4H()); in TEST() local
3776 __ Fmul(v9.V4H(), v0.V4H(), v1.V4H()); in TEST() local
3777 __ Fmul(v10.V4H(), v5.V4H(), v0.V4H()); in TEST() local
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| D | test-disasm-sve-aarch64.cc | 969 COMPARE_MACRO(Fmul(z1.VnS(), in TEST()
1066 COMPARE_MACRO(Fmul(z21.VnH(), p3.Merging(), z11.VnH(), 2.0), in TEST()
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| /external/swiftshader/third_party/subzero/crosstest/ |
| D | test_arith.def | 46 X(Fmul, *, ) \
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceInst.def | 41 X(Fmul, "fmul", 1) \
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| D | IceConverter.cpp | 301 return convertArithInstruction(Instr, Ice::InstArithmetic::Fmul); in convertInstruction()
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| D | IceTargetLoweringARM32.cpp | 2907 case InstArithmetic::Fmul: in lowerInt64Arithmetic()
3103 case InstArithmetic::Fmul: in lowerArithmetic()
3188 case InstArithmetic::Fmul: { in lowerArithmetic()
3509 case InstArithmetic::Fmul: in lowerArithmetic()
6924 case InstArithmetic::Fmul: in shouldTrackProducer()
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| D | WasmTranslator.cpp | 432 Control()->appendInst(InstArithmetic::create(Func, InstArithmetic::Fmul, in Binop()
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| D | IceTargetLoweringX86BaseImpl.h | 2113 case InstArithmetic::Fmul:
2259 case InstArithmetic::Fmul: {
2592 case InstArithmetic::Fmul:
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| D | PNaClTranslator.cpp | 1780 Op = Ice::InstArithmetic::Fmul; in convertBinopOpcode()
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| D | IceTargetLoweringMIPS32.cpp | 2721 case InstArithmetic::Fmul: in lowerInt64Arithmetic()
3003 case InstArithmetic::Fmul: in lowerArithmetic()
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| /external/vixl/benchmarks/aarch64/ |
| D | bench-utils.cc | 367 __ Fmul(PickV(size), PickV(size), PickV(size)); in GenerateFPSequence() local
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| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.h | 1627 void Fmul(const VRegister& vd, const VRegister& vn, const VRegister& vm) { in Fmul() function
2940 V(fmul, Fmul) \
4518 void Fmul(const ZRegister& zd, in Fmul() function
4526 void Fmul(const ZRegister& zd,
4531 void Fmul(const ZRegister& zd, in Fmul() function
4539 void Fmul(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) { in Fmul() function
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| D | macro-assembler-sve-aarch64.cc | 670 void MacroAssembler::Fmul(const ZRegister& zd, in Fmul() function in vixl::aarch64::MacroAssembler
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| /external/swiftshader/src/Reactor/ |
| D | SubzeroReactor.cpp | 1207 case Ice::InstArithmetic::Fmul: in isCommutative()
1275 return createArithmetic(Ice::InstArithmetic::Fmul, lhs, rhs); in createFMul()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 2411 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt); in ExpandLegalINT_TO_FP() local
2414 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2); in ExpandLegalINT_TO_FP()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 46952 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, VT, A, B, Flags); in combineFMA() local
46953 return DAG.getNode(ISD::FADD, dl, VT, Fmul, C, Flags); in combineFMA()
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