Searched refs:GEN11 (Results 1 – 4 of 4) sorted by relevance
| /external/mesa3d/src/intel/compiler/ |
| D | brw_gen_enum.h | 37 GEN11 = (1 << 9), enumerator
56 case 11: return GEN11; in gen_from_devinfo()
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| D | brw_eu.cpp | 618 { BRW_OPCODE_ROR, 14, "ror", 2, 1, GEN11 },
620 { BRW_OPCODE_ROL, 15, "rol", 2, 1, GEN11 },
686 { BRW_OPCODE_DP4, 84, "dp4", 2, 1, GEN_LT(GEN11) },
687 { BRW_OPCODE_DPH, 85, "dph", 2, 1, GEN_LT(GEN11) },
688 { BRW_OPCODE_DP3, 86, "dp3", 2, 1, GEN_LT(GEN11) },
689 { BRW_OPCODE_DP2, 87, "dp2", 2, 1, GEN_LT(GEN11) },
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| /external/igt-gpu-tools/tests/i915/ |
| D | gem_ctx_isolation.c | 57 #define GEN11 (ALL << 11) macro
139 { "CS_CHICKEN1", GEN11, RCS0, 0x2580, .masked = true },
160 { "VCS0_GPR", GEN11, VCS0, 0x1c0600, 32 },
161 { "VCS1_GPR", GEN11, VCS1, 0x1c4600, 32 },
162 { "VCS2_GPR", GEN11, VCS2, 0x1d0600, 32 },
163 { "VCS3_GPR", GEN11, VCS3, 0x1d4600, 32 },
164 { "VECS_GPR", GEN11, VECS0, 0x1c8600, 32 },
175 { "VCS0 timestamp", GEN11, ~0u, 0x1c0358 },
176 { "VCS1 timestamp", GEN11, ~0u, 0x1c4358 },
177 { "VCS2 timestamp", GEN11, ~0u, 0x1d0358 },
[all …]
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| /external/mesa3d/docs/relnotes/ |
| D | 19.1.0.rst | 3951 - i965: Re-enable fast color clears for GEN11.
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