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Searched refs:GEN7 (Results 1 – 6 of 6) sorted by relevance

/external/mesa3d/src/intel/compiler/
Dbrw_eu.cpp628 { BRW_OPCODE_F32TO16, 19, "f32to16", 1, 1, GEN7 | GEN75 },
629 { BRW_OPCODE_F16TO32, 20, "f16to32", 1, 1, GEN7 | GEN75 },
630 { BRW_OPCODE_BFREV, 23, "bfrev", 1, 1, GEN_GE(GEN7) & GEN_LT(GEN12) },
632 { BRW_OPCODE_BFE, 24, "bfe", 3, 1, GEN_GE(GEN7) & GEN_LT(GEN12) },
634 { BRW_OPCODE_BFI1, 25, "bfi1", 2, 1, GEN_GE(GEN7) & GEN_LT(GEN12) },
636 { BRW_OPCODE_BFI2, 26, "bfi2", 3, 1, GEN_GE(GEN7) & GEN_LT(GEN12) },
639 { BRW_OPCODE_BRD, 33, "brd", 0, 0, GEN_GE(GEN7) },
642 { BRW_OPCODE_BRC, 35, "brc", 0, 0, GEN_GE(GEN7) },
679 { BRW_OPCODE_FBH, 75, "fbh", 1, 1, GEN_GE(GEN7) },
680 { BRW_OPCODE_FBL, 76, "fbl", 1, 1, GEN_GE(GEN7) },
[all …]
Dbrw_gen_enum.h32 GEN7 = (1 << 4), enumerator
53 case 7: return devinfo->is_haswell ? GEN75 : GEN7; in gen_from_devinfo()
/external/igt-gpu-tools/tests/i915/
Dgem_ctx_isolation.c53 #define GEN7 (ALL << 7) macro
116 { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
117 { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
130 { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280, .write_mask = ~0x3 },
131 { "SO_WRITE_OFFSET1", GEN7, RCS0, 0x5284, .write_mask = ~0x3 },
132 { "SO_WRITE_OFFSET2", GEN7, RCS0, 0x5288, .write_mask = ~0x3 },
133 { "SO_WRITE_OFFSET3", GEN7, RCS0, 0x528c, .write_mask = ~0x3 },
169 { "BCS timestamp", GEN7, ~0u, 0x22358 },
/external/mesa3d/docs/relnotes/
D17.3.9.rst41 - GEN7: rendering issue on citra
D18.0.1.rst42 - GEN7: rendering issue on citra
D18.1.0.rst194 - GEN7: rendering issue on citra