| /external/arm-trusted-firmware/include/drivers/st/ |
| D | stm32mp1_rcc.h | 237 #define RCC_OFFSET_MASK GENMASK(11, 0)
244 #define RCC_SELR_SRC_MASK GENMASK(2, 0)
245 #define RCC_SELR_REFCLK_SRC_MASK GENMASK(1, 0)
253 #define RCC_MPCKSELR_MPUSRC_MASK GENMASK(1, 0)
271 #define RCC_CPERCKSELR_PERSRC_MASK GENMASK(1, 0)
275 #define RCC_DIVR_DIV_MASK GENMASK(5, 0)
279 #define RCC_APBXDIV_MASK GENMASK(2, 0)
280 #define RCC_MPUDIV_MASK GENMASK(2, 0)
281 #define RCC_AXIDIV_MASK GENMASK(2, 0)
282 #define RCC_MCUDIV_MASK GENMASK(3, 0)
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| D | stm32_uart_regs.h | 43 #define USART_CR1_DEDT GENMASK(20, 16)
49 #define USART_CR1_DEAT GENMASK(25, 21)
72 #define USART_CR2_STOP GENMASK(13, 12)
82 #define USART_CR2_ABRMODE GENMASK(22, 21)
86 #define USART_CR2_ADD GENMASK(31, 24)
105 #define USART_CR3_SCARCNT GENMASK(19, 17)
109 #define USART_CR3_WUS GENMASK(21, 20)
115 #define USART_CR3_RXFTCFG GENMASK(27, 25)
120 #define USART_CR3_TXFTCFG GENMASK(31, 29)
126 #define USART_BRR_DIV_FRACTION GENMASK(3, 0)
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| D | stm32_i2c.h | 23 #define I2C_CR1_DNF GENMASK(11, 8)
38 #define I2C_CR2_SADD GENMASK(9, 0)
46 #define I2C_CR2_NBYTES GENMASK(23, 16)
53 #define I2C_OAR1_OA1 GENMASK(9, 0)
58 #define I2C_OAR2_OA2 GENMASK(7, 1)
59 #define I2C_OAR2_OA2MSK GENMASK(10, 8)
63 #define I2C_OAR2_OA2MASK03 GENMASK(9, 8)
67 #define I2C_OAR2_OA2MASK07 GENMASK(10, 8)
71 #define I2C_TIMINGR_SCLL GENMASK(7, 0)
72 #define I2C_TIMINGR_SCLH GENMASK(15, 8)
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| D | stm32mp1_ddr_regs.h | 258 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12)
264 #define DDRCTRL_STAT_OPERATING_MODE_MASK GENMASK(2, 0)
267 #define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4)
277 #define DDRCTRL_MRCTRL0_MR_ADDR_MASK GENMASK(15, 12)
287 #define DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK GENMASK(23, 16)
294 #define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK GENMASK(27, 16)
297 #define DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK GENMASK(31, 30)
307 #define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH GENMASK(12, 8)
308 #define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH GENMASK(4, 0)
358 #define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7)
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| D | bsec.h | 18 #define BSEC_OTP_MASK GENMASK(4, 0)
24 #define DATA_LOWER_OTP_PERLOCK_MASK GENMASK(2, 0)
27 #define DATA_UPPER_OTP_PERLOCK_MASK GENMASK(3, 0)
83 #define BSEC_CONF_FRQ_MASK GENMASK(2, 1)
85 #define BSEC_CONF_PRG_WIDTH_MASK GENMASK(6, 3)
87 #define BSEC_CONF_TREAD_MASK GENMASK(8, 7)
110 #define BSEC_MODE_STATUS_MASK GENMASK(2, 0)
128 #define BSEC_DEN_ALL_MSK GENMASK(10, 0)
131 #define BSEC_FEN_ALL_MSK GENMASK(14, 0)
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| /external/arm-trusted-firmware/drivers/st/etzpc/ |
| D | etzpc.c | 25 #define ETZPC_MODE_MASK GENMASK(1, 0)
27 #define ETZPC_ID_MASK GENMASK(7, 0)
38 #define ETZPC_DECPROT0_MASK GENMASK(1, 0)
74 #define PERIPH_ATTR_MASK GENMASK(2, 0)
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| /external/arm-trusted-firmware/include/drivers/ |
| D | mmc.h | 36 #define OCR_VDD_MIN_2V7 GENMASK(23, 15)
37 #define OCR_VDD_MIN_2V0 GENMASK(14, 8)
86 #define CSD_TRAN_SPEED_UNIT_MASK GENMASK(2, 0)
87 #define CSD_TRAN_SPEED_MULT_MASK GENMASK(6, 3)
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| D | raw_nand.h | 59 #define NAND_REQ_MASK GENMASK(14, 12)
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| /external/arm-trusted-firmware/drivers/st/reset/ |
| D | stm32mp1_reset.c | 21 return ((reset_id & GENMASK(31, 5)) >> 5) * sizeof(uint32_t); in id2reg_offset()
26 return (uint8_t)(reset_id & GENMASK(4, 0)); in id2reg_bit_pos()
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| /external/arm-trusted-firmware/drivers/allwinner/ |
| D | sunxi_msgbox.c | 26 #define FIFO_STAT_MASK GENMASK(0, 0)
29 #define MSG_STAT_MASK GENMASK(2, 0)
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| /external/arm-trusted-firmware/plat/mediatek/mt8192/drivers/mcdi/ |
| D | mt_cpu_pm_cpc.c | 76 uint32_t cnt_mask = GENMASK(14, 0); in mtk_cpc_cluster_cnt_backup()
77 uint32_t clr_mask = GENMASK(1, 0); in mtk_cpc_cluster_cnt_backup()
191 val = GENMASK(1, 0); /* clr_mask */ in mtk_cpc_config()
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| D | mt_mcdi.c | 36 #define MCUPM_PWR_CTRL_MASK GENMASK(3, 0)
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| /external/arm-trusted-firmware/drivers/scmi-msg/ |
| D | clock.h | 28 #define SCMI_CLOCK_CLOCK_COUNT_MASK GENMASK(15, 0)
29 #define SCMI_CLOCK_MAX_PENDING_TRANSITIONS_MASK GENMASK(23, 16)
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| /external/arm-trusted-firmware/drivers/st/gpio/ |
| D | stm32_gpio.c | 23 #define DT_GPIO_BANK_MASK GENMASK(16, 12)
25 #define DT_GPIO_PIN_MASK GENMASK(11, 8)
26 #define DT_GPIO_MODE_MASK GENMASK(7, 0)
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| /external/arm-trusted-firmware/include/lib/ |
| D | utils_def.h | 51 #define GENMASK GENMASK_64 macro
53 #define GENMASK GENMASK_32 macro
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| /external/arm-trusted-firmware/plat/mediatek/mt8192/drivers/spmc/ |
| D | mtspmc_private.h | 137 #define CORE_SPMC_PWR_ON_ACK GENMASK(15, 0)
164 #define ILDO_RET_VOSEL GENMASK(7, 0)
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| /external/arm-trusted-firmware/drivers/st/mmc/ |
| D | stm32_sdmmc2.c | 52 #define SDMMC_POWER_PWRCTRL GENMASK(1, 0)
65 #define SDMMC_CMDR_WAITRESP GENMASK(9, 8)
73 #define SDMMC_DCTRLR_DTMODE GENMASK(3, 2)
74 #define SDMMC_DCTRLR_DBLOCKSIZE GENMASK(7, 4)
544 assert((buf & GENMASK(1, 0)) == 0U); in stm32_sdmmc2_read()
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| /external/kernel-headers/original/uapi/linux/ |
| D | cxl_mem.h | 78 #define CXL_MEM_COMMAND_FLAG_MASK GENMASK(0, 0)
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| D | v4l2-controls.h | 1622 #define V4L2_FWHT_FL_COMPONENTS_NUM_MSK GENMASK(18, 16)
1626 #define V4L2_FWHT_FL_PIXENC_MSK GENMASK(20, 19)
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| /external/kernel-headers/original/uapi/asm-x86/asm/ |
| D | kvm_para.h | 91 #define KVM_ASYNC_PF_VEC_MASK GENMASK(7, 0)
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| /external/arm-trusted-firmware/plat/socionext/uniphier/ |
| D | uniphier_psci.c | 20 #define UNIPHIER_SLFRSTSEL_MASK GENMASK(1, 0)
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| /external/arm-trusted-firmware/drivers/st/pmic/ |
| D | stm32mp_pmic.c | 21 #define STPMIC1_LDO12356_OUTPUT_MASK (uint8_t)(GENMASK(6, 2))
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| /external/arm-trusted-firmware/plat/ti/k3/common/drivers/sec_proxy/ |
| D | sec_proxy.c | 28 #define RT_THREAD_STATUS_CUR_CNT_MASK GENMASK(7, 0)
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| /external/arm-trusted-firmware/drivers/st/crypto/ |
| D | stm32_hash.c | 46 #define HASH_STR_NBLW_MASK GENMASK(4, 0)
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| /external/arm-trusted-firmware/drivers/mtd/nand/ |
| D | raw_nand.c | 248 crc &= GENMASK(15, 0); in nand_check_crc()
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