Searched refs:GICC_AHPPIR (Results 1 – 16 of 16) sorted by relevance
| /external/arm-trusted-firmware/plat/amlogic/common/include/ |
| D | plat_macros.S | 40 ldr w9, [x17, #GICC_AHPPIR]
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| /external/arm-trusted-firmware/plat/nvidia/tegra/include/ |
| D | plat_macros.S | 38 ldr w9, [x16, #GICC_AHPPIR]
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| /external/arm-trusted-firmware/plat/mediatek/mt8183/include/ |
| D | plat_macros.S | 41 ldr w9, [x27, #GICC_AHPPIR]
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| /external/arm-trusted-firmware/plat/mediatek/mt8173/include/ |
| D | plat_macros.S | 41 ldr w9, [x17, #GICC_AHPPIR]
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| /external/arm-trusted-firmware/plat/mediatek/mt6795/include/ |
| D | plat_macros.S | 35 ldr w9, [x17, #GICC_AHPPIR]
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| /external/arm-trusted-firmware/plat/hisilicon/hikey960/include/ |
| D | plat_macros.S | 43 ldr w9, [x17, #GICC_AHPPIR]
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| /external/arm-trusted-firmware/plat/hisilicon/hikey/include/ |
| D | plat_macros.S | 43 ldr w9, [x17, #GICC_AHPPIR]
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| /external/arm-trusted-firmware/plat/renesas/common/include/ |
| D | plat_macros.S | 38 ldr w9, [x17, #GICC_AHPPIR]
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| /external/arm-trusted-firmware/plat/qti/common/inc/aarch64/ |
| D | plat_macros.S | 77 ldr w9, [x27, #GICC_AHPPIR]
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| /external/arm-trusted-firmware/plat/xilinx/versal/include/ |
| D | plat_macros.S | 68 ldr w9, [x17, #GICC_AHPPIR]
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| /external/arm-trusted-firmware/include/plat/arm/common/aarch64/ |
| D | arm_macros.S | 68 ldr w9, [x17, #GICC_AHPPIR]
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| /external/arm-trusted-firmware/include/plat/marvell/armada/common/aarch64/ |
| D | marvell_macros.S | 77 ldr w9, [x17, #GICC_AHPPIR]
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| /external/arm-trusted-firmware/plat/rockchip/common/include/ |
| D | plat_macros.S | 76 ldr w9, [x27, #GICC_AHPPIR]
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| /external/arm-trusted-firmware/drivers/arm/gic/v2/ |
| D | gicv2_private.h | 92 return mmio_read_32(base + GICC_AHPPIR); in gicc_read_ahppir()
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| /external/arm-trusted-firmware/include/drivers/arm/ |
| D | gicv2.h | 65 #define GICC_AHPPIR U(0x28) macro
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| /external/arm-trusted-firmware/docs/getting_started/ |
| D | porting-guide.rst | 2615 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt.
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