/external/arm-trusted-firmware/plat/renesas/common/aarch64/ |
D | platform_common.c | 224 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 227 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 229 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 231 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 233 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 235 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 237 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 239 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 241 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 243 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), [all …]
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/external/arm-trusted-firmware/plat/amlogic/gxbb/ |
D | gxbb_bl31_setup.c | 108 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 110 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 112 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 114 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 116 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 118 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 120 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 122 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 124 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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/external/arm-trusted-firmware/plat/amlogic/g12a/ |
D | g12a_bl31_setup.c | 108 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 110 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 112 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 114 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 116 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 118 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 120 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 122 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 124 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
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/external/arm-trusted-firmware/plat/amlogic/gxl/ |
D | gxl_bl31_setup.c | 124 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 126 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 128 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 130 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 132 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 134 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 136 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 138 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 140 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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/external/arm-trusted-firmware/plat/amlogic/axg/ |
D | axg_bl31_setup.c | 134 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 136 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 138 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 140 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 142 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 144 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 146 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 148 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 150 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
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/external/arm-trusted-firmware/plat/qemu/common/ |
D | qemu_gicv2.c | 12 PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0), 13 PLATFORM_G0_PROPS(GICV2_INTR_GROUP0)
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/external/arm-trusted-firmware/plat/hisilicon/poplar/ |
D | poplar_gicv2.c | 17 POPLAR_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), 18 POPLAR_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
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/external/arm-trusted-firmware/plat/arm/common/ |
D | arm_gicv2.c | 28 PLAT_ARM_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), 29 PLAT_ARM_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
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/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t210/ |
D | plat_setup.c | 192 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 194 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 196 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
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/external/arm-trusted-firmware/plat/rockchip/rk3288/ |
D | rk3288_def.h | 123 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), \ 125 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
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/external/arm-trusted-firmware/plat/marvell/armada/common/ |
D | marvell_gicv2.c | 46 PLAT_MARVELL_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), 47 PLAT_MARVELL_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
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/external/arm-trusted-firmware/plat/rockchip/rk3328/ |
D | rk3328_def.h | 143 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), \ 145 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
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/external/arm-trusted-firmware/plat/hisilicon/hikey/ |
D | hikey_bl31_setup.c | 38 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 40 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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/external/arm-trusted-firmware/plat/rockchip/px30/ |
D | px30_def.h | 165 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), \ 167 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
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/external/arm-trusted-firmware/plat/qemu/common/sp_min/ |
D | sp_min_setup.c | 55 PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0), 56 PLATFORM_G0_PROPS(GICV2_INTR_GROUP0)
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/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/ |
D | plat_setup.c | 237 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 239 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 241 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
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/external/arm-trusted-firmware/plat/intel/soc/agilex/ |
D | bl31_plat_setup.c | 84 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), 85 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
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/external/arm-trusted-firmware/plat/hisilicon/hikey960/ |
D | hikey960_bl31_setup.c | 40 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 42 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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D | hikey960_bl1_setup.c | 52 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 54 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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/external/arm-trusted-firmware/plat/intel/soc/stratix10/ |
D | bl31_plat_setup.c | 92 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), 93 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
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/external/arm-trusted-firmware/drivers/arm/gic/v2/ |
D | gicv2_helpers.c | 139 assert(prop_desc->intr_grp == GICV2_INTR_GROUP0); in gicv2_secure_spis_configure_props() 192 assert(prop_desc->intr_grp == GICV2_INTR_GROUP0); in gicv2_secure_ppi_sgi_setup_props()
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/external/arm-trusted-firmware/plat/mediatek/mt6795/ |
D | plat_mt_gic.c | 15 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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/external/arm-trusted-firmware/plat/layerscape/common/tsp/ |
D | ls_tsp_setup.c | 18 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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/external/arm-trusted-firmware/plat/rockchip/rk3368/ |
D | rk3368_def.h | 114 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
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/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t194/ |
D | plat_setup.c | 348 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 350 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
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