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Searched refs:GPR64 (Results 1 – 25 of 67) sorted by relevance

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/external/llvm/lib/Target/AArch64/
DAArch64InstrAtomics.td48 def : Pat<(relaxed_load<atomic_load_8> (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
50 (LDRBBroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$offset)>;
63 def : Pat<(relaxed_load<atomic_load_16> (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
65 (LDRHHroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend)>;
78 def : Pat<(relaxed_load<atomic_load_32> (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
80 (LDRWroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend)>;
93 def : Pat<(relaxed_load<atomic_load_64> (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
95 (LDRXroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
135 (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend),
137 (STRBBroX GPR32:$val, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend)>;
[all …]
DAArch64InstrInfo.td333 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
334 [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>,
340 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
341 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi),
345 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
346 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi),
350 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
351 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi),
355 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
356 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi),
[all …]
DAArch64RegisterInfo.td129 // GPR64/GPR64sp for use by the coalescer.
144 def GPR64 : RegisterClass<"AArch64", [i64], 64, (add GPR64common, XZR)> {
145 let AltOrders = [(rotl GPR64, 8)];
191 def GPR64pi1 : RegisterOperand<GPR64, "printPostIncOperand<1>">;
192 def GPR64pi2 : RegisterOperand<GPR64, "printPostIncOperand<2>">;
193 def GPR64pi3 : RegisterOperand<GPR64, "printPostIncOperand<3>">;
194 def GPR64pi4 : RegisterOperand<GPR64, "printPostIncOperand<4>">;
195 def GPR64pi6 : RegisterOperand<GPR64, "printPostIncOperand<6>">;
196 def GPR64pi8 : RegisterOperand<GPR64, "printPostIncOperand<8>">;
197 def GPR64pi12 : RegisterOperand<GPR64, "printPostIncOperand<12>">;
[all …]
DAArch64InstrFormats.td592 def arith_shifted_reg64 : arith_shifted_reg<i64, GPR64, 64>;
614 def logical_shifted_reg64 : logical_shifted_reg<i64, GPR64, logical_shift64>;
930 class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
939 class MSRI : RtSystemI<0, (outs), (ins msr_sysreg_op:$systemreg, GPR64:$Rt),
1014 (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, GPR64:$Rt),
1029 (ins GPR64:$Rt, imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2),
1063 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> {
1147 def X : BaseCmpBranch<GPR64, op, asm, node> {
1219 def X : BaseTestBranch<GPR64, tbz_imm32_63, op, asm, node> {
1227 def : Pat<(node GPR64:$Rn, tbz_imm0_31_diag:$imm, bb:$target),
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrAtomics.td50 def : Pat<(relaxed_load<atomic_load_8> (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
52 (LDRBBroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$offset)>;
65 def : Pat<(relaxed_load<atomic_load_16> (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
67 (LDRHHroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend)>;
80 def : Pat<(relaxed_load<atomic_load_32> (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
82 (LDRWroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend)>;
95 def : Pat<(relaxed_load<atomic_load_64> (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
97 (LDRXroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
135 (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend),
137 (STRBBroX GPR32:$val, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend)>;
[all …]
DAArch64InstrInfo.td608 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
609 [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>,
615 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
616 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi),
620 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
621 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi),
625 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
626 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi),
630 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
631 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi),
[all …]
DAArch64InstrFormats.td209 def GPR64as32 : RegisterOperand<GPR64, "printGPR64as32"> {
868 def arith_shifted_reg64 : arith_shifted_reg<i64, GPR64, 64>;
898 def logical_shifted_reg64 : logical_shifted_reg<i64, GPR64, logical_shift64>;
1199 (outs GPR64:$Rt), (ins), asm, "\t$Rt", pattern> {
1321 class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
1330 class MSRI : RtSystemI<0, (outs), (ins msr_sysreg_op:$systemreg, GPR64:$Rt),
1411 (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, GPR64:$Rt),
1426 (ins GPR64:$Rt, imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2),
1460 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> {
1494 : AuthBase<M, (outs), (ins GPR64:$Rn, GPR64sp:$Rm), asm, "\t$Rn, $Rm", []> {
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64InstrAtomics.td50 def : Pat<(relaxed_load<atomic_load_8> (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
52 (LDRBBroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$offset)>;
65 def : Pat<(relaxed_load<atomic_load_16> (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
67 (LDRHHroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend)>;
80 def : Pat<(relaxed_load<atomic_load_32> (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
82 (LDRWroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend)>;
95 def : Pat<(relaxed_load<atomic_load_64> (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
97 (LDRXroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
135 (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend),
137 (STRBBroX GPR32:$val, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend)>;
[all …]
DAArch64InstrInfo.td641 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
642 [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>,
648 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
649 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi),
653 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
654 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi),
658 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
659 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi),
663 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
664 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi),
[all …]
DAArch64SVEInstrInfo.td1069 (RegImmInst sve_prfop:$prfop, PPR_3b:$gp, GPR64:$base, simm6s1:$offset)>;
1074 …def _reg_reg : Pat<(prefetch (PredTy PPR_3b:$gp), (AddrCP GPR64sp:$base, GPR64:$index), (i32 sve_p…
1075 (RegRegInst sve_prfop:$prfop, PPR_3b:$gp, GPR64:$base, GPR64:$index)>;
1079 def _default : Pat<(prefetch (PredTy PPR_3b:$gp), GPR64:$base, (i32 sve_prfop:$prfop)),
1080 (RegImmInst sve_prfop:$prfop, PPR_3b:$gp, GPR64:$base, (i64 0))>;
1282 def CTERMEQ_XX : sve_int_cterm<0b1, 0b0, "ctermeq", GPR64>;
1283 def CTERMNE_XX : sve_int_cterm<0b1, 0b1, "ctermne", GPR64>;
1644 def : Pat<(nxv16i8 (AArch64ld1rq_z PPR:$gp, GPR64:$base)),
1646 def : Pat<(nxv8i16 (AArch64ld1rq_z PPR:$gp, GPR64:$base)),
1648 def : Pat<(nxv4i32 (AArch64ld1rq_z PPR:$gp, GPR64:$base)),
[all …]
DAArch64RegisterInfo.td140 // GPR64/GPR64sp for use by the coalescer.
155 def GPR64 : RegisterClass<"AArch64", [i64], 64, (add GPR64common, XZR)> {
156 let AltOrders = [(rotl GPR64, 8)];
184 // GPR32/GPR64 but with zero-register substitution enabled.
185 // TODO: Roll this out to GPR32/GPR64/GPR32all/GPR64all.
189 def GPR64z : RegisterOperand<GPR64> {
218 def GPR64noip : RegisterClass<"AArch64", [i64], 64, (sub GPR64, X16, X17, LR)>;
227 def GPR64pi1 : RegisterOperand<GPR64, "printPostIncOperand<1>">;
228 def GPR64pi2 : RegisterOperand<GPR64, "printPostIncOperand<2>">;
229 def GPR64pi3 : RegisterOperand<GPR64, "printPostIncOperand<3>">;
[all …]
/external/llvm/test/CodeGen/Mips/
Ddivrem.ll6 …ify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR64,GPR64-TRAP
13 …mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR64,NOCHECK
20 ; GPR64 - Same as GPR32 but only for 64-bit targets
24 ; GPR64-TRAP - Same as TRAP and GPR64 combined
43 ; GPR64: div $2, $4, $5
44 ; GPR64-TRAP: teq $5, $zero, 7
70 ; GPR64: mod $2, $4, $5
71 ; GPR64-TRAP: teq $5, $zero, 7
97 ; GPR64: divu $2, $4, $5
98 ; GPR64-TRAP: teq $5, $zero, 7
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/
Ddivrem.ll6 …ify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR64,GPR64-TRAP
13 …mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR64,NOCHECK
20 ; GPR64 - Same as GPR32 but only for 64-bit targets
24 ; GPR64-TRAP - Same as TRAP and GPR64 combined
43 ; GPR64: div $2, $4, $5
44 ; GPR64-TRAP: teq $5, $zero, 7
70 ; GPR64: mod $2, $4, $5
71 ; GPR64-TRAP: teq $5, $zero, 7
97 ; GPR64: divu $2, $4, $5
98 ; GPR64-TRAP: teq $5, $zero, 7
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMips64InstrInfo.td78 def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>;
79 def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>;
80 def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>;
81 def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>;
82 def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>;
83 def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>;
84 def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>;
85 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>;
86 def ATOMIC_LOAD_MIN_I64 : Atomic2Ops<atomic_load_min_64, GPR64>;
87 def ATOMIC_LOAD_MAX_I64 : Atomic2Ops<atomic_load_max_64, GPR64>;
[all …]
DMipsCondMov.td204 defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>,
206 defm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64, SLTiu64>,
208 defm : MovzPats0<GPR64, GPR64, MOVZ_I_I64, SLT64, SLTu64, SLTi64, SLTiu64>,
210 defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>,
212 defm : MovzPats1<GPR64, GPR32, MOVZ_I64_I, XOR64>,
214 defm : MovzPats1<GPR64, GPR64, MOVZ_I64_I64, XOR64>,
216 defm : MovzPats2<GPR32, GPR64, MOVZ_I_I64, XORi>,
218 defm : MovzPats2<GPR64, GPR32, MOVZ_I64_I, XORi64>,
220 defm : MovzPats2<GPR64, GPR64, MOVZ_I64_I64, XORi64>,
225 defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
[all …]
/external/llvm/lib/Target/Mips/
DMips64InstrInfo.td74 def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>;
75 def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>;
76 def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>;
77 def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>;
78 def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>;
79 def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>;
80 def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>;
81 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>;
281 def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>,
283 def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>,
[all …]
DMicroMips64r6InstrInfo.td436 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)),
437 (DADDIU_MM64R6 GPR64:$hi, tglobaladdr:$lo)>, ISA_MICROMIPS64R6;
438 def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)),
439 (DADDIU_MM64R6 GPR64:$hi, tblockaddress:$lo)>, ISA_MICROMIPS64R6;
440 def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)),
441 (DADDIU_MM64R6 GPR64:$hi, tjumptable:$lo)>, ISA_MICROMIPS64R6;
442 def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)),
443 (DADDIU_MM64R6 GPR64:$hi, tconstpool:$lo)>, ISA_MICROMIPS64R6;
444 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)),
445 (DADDIU_MM64R6 GPR64:$hi, tglobaltlsaddr:$lo)>, ISA_MICROMIPS64R6;
[all …]
DMipsCondMov.td204 defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>,
206 defm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64, SLTiu64>,
208 defm : MovzPats0<GPR64, GPR64, MOVZ_I_I64, SLT64, SLTu64, SLTi64, SLTiu64>,
210 defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>,
212 defm : MovzPats1<GPR64, GPR32, MOVZ_I64_I, XOR64>,
214 defm : MovzPats1<GPR64, GPR64, MOVZ_I64_I64, XOR64>,
216 defm : MovzPats2<GPR32, GPR64, MOVZ_I_I64, XORi>,
218 defm : MovzPats2<GPR64, GPR32, MOVZ_I64_I, XORi64>,
220 defm : MovzPats2<GPR64, GPR64, MOVZ_I64_I64, XORi64>,
225 defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
[all …]
/external/llvm-project/llvm/lib/Target/Mips/
DMips64InstrInfo.td78 def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>;
79 def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>;
80 def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>;
81 def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>;
82 def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>;
83 def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>;
84 def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>;
85 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>;
86 def ATOMIC_LOAD_MIN_I64 : Atomic2Ops<atomic_load_min_64, GPR64>;
87 def ATOMIC_LOAD_MAX_I64 : Atomic2Ops<atomic_load_max_64, GPR64>;
[all …]
DMipsCondMov.td204 defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>,
206 defm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64, SLTiu64>,
208 defm : MovzPats0<GPR64, GPR64, MOVZ_I_I64, SLT64, SLTu64, SLTi64, SLTiu64>,
210 defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>,
212 defm : MovzPats1<GPR64, GPR32, MOVZ_I64_I, XOR64>,
214 defm : MovzPats1<GPR64, GPR64, MOVZ_I64_I64, XOR64>,
216 defm : MovzPats2<GPR32, GPR64, MOVZ_I_I64, XORi>,
218 defm : MovzPats2<GPR64, GPR32, MOVZ_I64_I, XORi64>,
220 defm : MovzPats2<GPR64, GPR64, MOVZ_I64_I64, XORi64>,
225 defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/llvm-ir/
Dret.ll15 …rch=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
16 …rch=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
17 …rch=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
18 …rch=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
19 …rch=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
26 …6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C
116 ; GPR64-DAG: ori $2, $[[T0]], 1
131 ; GPR64-DAG: daddiu $[[T1:[0-9]+]], $[[T0]], 1
132 ; GPR64-DAG: dsll $2, $[[T1]], 32
147 ; GPR64-DAG: ori $[[T0:[0-9]+]], $zero, 32769
[all …]
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dret.ll15 …rch=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
16 …rch=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
17 …rch=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
18 …rch=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
19 …rch=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
26 …6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C
116 ; GPR64-DAG: daddiu $2, $[[T0]], 1
131 ; GPR64-DAG: daddiu $[[T1:[0-9]+]], $[[T0]], 1
132 ; GPR64-DAG: dsll $2, $[[T1]], 32
147 ; GPR64-DAG: ori $[[T0:[0-9]+]], $zero, 32769
[all …]
/external/llvm-project/llvm/test/TableGen/
Drc-weight-override.td10 def GPR_64_W0 : RegisterClass<"", [v2i32], 64, (add GPR64)> {
15 def GPR_64_W1 : RegisterClass<"", [v2i32], 64, (add GPR64)> {
20 def GPR_64_W8 : RegisterClass<"", [v2i32], 64, (add GPR64)> {
Dambiguous-composition.td78 class GPR64<string n, GPR32 low> : TestReg<n, [low]> {
82 class GPR128<string n, GPR64 low> : TestReg<n, [low]> {
87 def G0D : GPR64<"g0d", G0S>;
/external/capstone/arch/AArch64/
DAArch64GenAsmWriter.inc7192 // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, 0)
7202 // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh)
7215 // (ADDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0)
7241 // (ADDSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24)
7251 // (ADDSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh)
7264 // (ADDSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24)
7378 // (ADDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0)
7393 // (ADDXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24)
7406 // (ADDXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24)
7463 // (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2)
[all …]

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