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Searched refs:GPRRegBankID (Results 1 – 17 of 17) sorted by relevance

/external/llvm/lib/Target/AArch64/
DAArch64RegisterBankInfo.cpp31 createRegisterBank(AArch64::GPRRegBankID, "GPR"); in AArch64RegisterBankInfo()
34 addRegBankCoverage(AArch64::GPRRegBankID, AArch64::GPR64allRegClassID, TRI); in AArch64RegisterBankInfo()
35 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
108 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
141 getRegBank(AArch64::GPRRegBankID)); in getInstrAlternativeMappings()
DAArch64RegisterBankInfo.h25 GPRRegBankID = 0, /// General Purpose Registers: W, X. enumerator
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstructionSelector.cpp193 assert((RegBank->getID() == ARM::GPRRegBankID || in guessRegClass()
248 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
253 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
275 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
280 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
360 if (RegBank == ARM::GPRRegBankID) { in selectLoadStoreOpCode()
532 if (!validReg(MRI, ResReg, 1, ARM::GPRRegBankID)) in selectCmp()
775 assert(validReg(MRI, CondReg, 1, ARM::GPRRegBankID) && in selectSelect()
789 assert(validOpRegPair(MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) && in selectSelect()
790 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) && in selectSelect()
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DARMRegisterBankInfo.cpp57 checkPartMapping(PartMappings[PMI_GPR - PMI_Min], 0, 32, GPRRegBankID) && in checkPartialMappings()
142 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID); in ARMRegisterBankInfo()
198 return getRegBank(ARM::GPRRegBankID); in getRegBankFromRegClass()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstructionSelector.cpp195 assert((RegBank->getID() == ARM::GPRRegBankID || in guessRegClass()
250 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
255 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
277 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
282 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
362 if (RegBank == ARM::GPRRegBankID) { in selectLoadStoreOpCode()
534 if (!validReg(MRI, ResReg, 1, ARM::GPRRegBankID)) in selectCmp()
777 assert(validReg(MRI, CondReg, 1, ARM::GPRRegBankID) && in selectSelect()
791 assert(validOpRegPair(MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) && in selectSelect()
792 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) && in selectSelect()
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DARMRegisterBankInfo.cpp57 checkPartMapping(PartMappings[PMI_GPR - PMI_Min], 0, 32, GPRRegBankID) && in checkPartialMappings()
144 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID); in ARMRegisterBankInfo()
196 return getRegBank(ARM::GPRRegBankID); in getRegBankFromRegClass()
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenRegisterBank.inc15 GPRRegBankID,
95 RegisterBank GPRRegBank(/* ID */ ARM::GPRRegBankID, /* Name */ "GPRB", /* Size */ 32, /* CoveredReg…
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenRegisterBank.inc16 GPRRegBankID,
119 RegisterBank GPRRegBank(/* ID */ AArch64::GPRRegBankID, /* Name */ "GPR", /* Size */ 64, /* Covered…
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64RegisterBankInfo.cpp51 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
260 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
313 getCopyMapping(AArch64::GPRRegBankID, AArch64::GPRRegBankID, Size), in getInstrAlternativeMappings()
322 getCopyMapping(AArch64::FPRRegBankID, AArch64::GPRRegBankID, Size), in getInstrAlternativeMappings()
327 getCopyMapping(AArch64::GPRRegBankID, AArch64::FPRRegBankID, Size), in getInstrAlternativeMappings()
DAArch64InstructionSelector.cpp335 if (RB.getID() == AArch64::GPRRegBankID) { in getRegClassForTypeOnBank()
367 if (RegBankID == AArch64::GPRRegBankID) { in getMinClassForRegBank()
479 case AArch64::GPRRegBankID: in selectBinaryOp()
551 case AArch64::GPRRegBankID: in selectLoadStoreUIOp()
747 if (DstRegBank.getID() == AArch64::GPRRegBankID && DstSize == 32 && in selectCopy()
863 AArch64::GPRRegBankID); in selectSelectOpc()
1012 if (RB.getID() != AArch64::GPRRegBankID) in selectCompareBranch()
1281 MRI.setRegBank(Trunc.getReg(0), RBI.getRegBank(AArch64::GPRRegBankID)); in preISelLower()
1624 if (RB.getID() != AArch64::GPRRegBankID) { in select()
1844 assert(PtrRB.getID() == AArch64::GPRRegBankID && in select()
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/external/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64RegisterBankInfo.cpp51 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
268 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
321 getCopyMapping(AArch64::GPRRegBankID, AArch64::GPRRegBankID, Size), in getInstrAlternativeMappings()
330 getCopyMapping(AArch64::FPRRegBankID, AArch64::GPRRegBankID, Size), in getInstrAlternativeMappings()
335 getCopyMapping(AArch64::GPRRegBankID, AArch64::FPRRegBankID, Size), in getInstrAlternativeMappings()
DAArch64InstructionSelector.cpp461 if (RB.getID() == AArch64::GPRRegBankID) { in getRegClassForTypeOnBank()
493 if (RegBankID == AArch64::GPRRegBankID) { in getMinClassForRegBank()
553 case AArch64::GPRRegBankID: in getMinSizeForRegBank()
638 case AArch64::GPRRegBankID: in selectBinaryOp()
710 case AArch64::GPRRegBankID: in selectLoadStoreUIOp()
1026 if (RBI.getRegBank(True, MRI, TRI)->getID() != AArch64::GPRRegBankID) { in emitSelect()
1463 AArch64::GPRRegBankID && in emitCBZ()
1907 MRI.setRegBank(Trunc.getReg(0), RBI.getRegBank(AArch64::GPRRegBankID)); in preISelLower()
1937 MRI.setRegBank(NewSrc.getReg(0), RBI.getRegBank(AArch64::GPRRegBankID)); in preISelLower()
1970 MRI.setRegBank(PtrToInt.getReg(0), RBI.getRegBank(AArch64::GPRRegBankID)); in convertPtrAddToAdd()
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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenRegisterBank.inc14 GPRRegBankID,
137 RegisterBank GPRRegBank(/* ID */ X86::GPRRegBankID, /* Name */ "GPR", /* Size */ 64, /* CoveredRegC…
/external/llvm-project/llvm/lib/Target/X86/
DX86InstructionSelector.cpp171 if (RB.getID() == X86::GPRRegBankID) { in getRegClass()
245 if (DstSize > SrcSize && SrcRegBank.getID() == X86::GPRRegBankID && in selectCopy()
246 DstRegBank.getID() == X86::GPRRegBankID) { in selectCopy()
281 if (SrcRegBank.getID() == X86::GPRRegBankID && in selectCopy()
282 DstRegBank.getID() == X86::GPRRegBankID && SrcSize > DstSize && in selectCopy()
405 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
408 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
411 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
421 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
643 if (RBI.getRegBank(DefReg, MRI, TRI)->getID() != X86::GPRRegBankID) in selectConstant()
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DX86RegisterBankInfo.cpp32 const RegisterBank &RBGPR = getRegBank(X86::GPRRegBankID); in X86RegisterBankInfo()
53 return getRegBank(X86::GPRRegBankID); in getRegBankFromRegClass()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstructionSelector.cpp170 if (RB.getID() == X86::GPRRegBankID) { in getRegClass()
244 if (DstSize > SrcSize && SrcRegBank.getID() == X86::GPRRegBankID && in selectCopy()
245 DstRegBank.getID() == X86::GPRRegBankID) { in selectCopy()
280 if (SrcRegBank.getID() == X86::GPRRegBankID && in selectCopy()
281 DstRegBank.getID() == X86::GPRRegBankID && SrcSize > DstSize && in selectCopy()
404 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
407 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
410 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
420 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
642 if (RBI.getRegBank(DefReg, MRI, TRI)->getID() != X86::GPRRegBankID) in selectConstant()
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DX86RegisterBankInfo.cpp32 const RegisterBank &RBGPR = getRegBank(X86::GPRRegBankID); in X86RegisterBankInfo()
53 return getRegBank(X86::GPRRegBankID); in getRegBankFromRegClass()