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1 /*
2  * Copyright 2020 NXP
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef GPC_REG_H
8 #define GPC_REG_H
9 
10 #define LPCR_A53_BSC			0x0
11 #define LPCR_A53_BSC2			0x108
12 #define LPCR_A53_AD			0x4
13 #define LPCR_M4				0x8
14 #define SLPCR				0x14
15 #define MST_CPU_MAPPING			0x18
16 #define MLPCR				0x20
17 #define PGC_ACK_SEL_A53			0x24
18 #define IMR1_CORE0_A53			0x30
19 #define IMR1_CORE1_A53			0x40
20 #define IMR1_CORE2_A53			0x1C0
21 #define IMR1_CORE3_A53			0x1D0
22 #define IMR1_CORE0_M4			0x50
23 #define SLT0_CFG			0xB0
24 #define GPC_PU_PWRHSK			0x1FC
25 #define PGC_CPU_0_1_MAPPING		0xEC
26 #define CPU_PGC_UP_TRG			0xF0
27 #define PU_PGC_UP_TRG			0xF8
28 #define CPU_PGC_DN_TRG			0xFC
29 #define PU_PGC_DN_TRG			0x104
30 #define LPS_CPU1			0x114
31 #define A53_CORE0_PGC			0x800
32 #define A53_PLAT_PGC			0x900
33 #define PLAT_PGC_PCR			0x900
34 #define NOC_PGC_PCR			0xa40
35 #define PGC_SCU_TIMING			0x910
36 
37 #define MASK_DSM_TRIGGER_A53		BIT(31)
38 #define IRQ_SRC_A53_WUP			BIT(30)
39 #define IRQ_SRC_A53_WUP_SHIFT		30
40 #define IRQ_SRC_C1			BIT(29)
41 #define IRQ_SRC_C0			BIT(28)
42 #define IRQ_SRC_C3			BIT(23)
43 #define IRQ_SRC_C2			BIT(22)
44 #define CPU_CLOCK_ON_LPM		BIT(14)
45 #define A53_CLK_ON_LPM			BIT(14)
46 #define MASTER0_LPM_HSK			BIT(6)
47 #define MASTER1_LPM_HSK			BIT(7)
48 #define MASTER2_LPM_HSK			BIT(8)
49 
50 #define L2PGE				BIT(31)
51 #define EN_L2_WFI_PDN			BIT(5)
52 #define EN_PLAT_PDN			BIT(4)
53 
54 #define SLPCR_EN_DSM			BIT(31)
55 #define SLPCR_RBC_EN			BIT(30)
56 #define SLPCR_A53_FASTWUP_STOP_MODE	BIT(17)
57 #define SLPCR_A53_FASTWUP_WAIT_MODE	BIT(16)
58 #define SLPCR_VSTBY			BIT(2)
59 #define SLPCR_SBYOS			BIT(1)
60 #define SLPCR_BYPASS_PMIC_READY		BIT(0)
61 #define SLPCR_RBC_COUNT_SHIFT		24
62 #define SLPCR_STBY_COUNT_SHFT		3
63 
64 #define A53_DUMMY_PDN_ACK		BIT(15)
65 #define A53_DUMMY_PUP_ACK		BIT(31)
66 #define A53_PLAT_PDN_ACK		BIT(2)
67 #define A53_PLAT_PUP_ACK		BIT(18)
68 #define NOC_PDN_SLT_CTRL		BIT(10)
69 #define NOC_PUP_SLT_CTRL		BIT(11)
70 #define NOC_PGC_PDN_ACK			BIT(3)
71 #define NOC_PGC_PUP_ACK			BIT(19)
72 
73 #define PLAT_PUP_SLT_CTRL		BIT(9)
74 #define PLAT_PDN_SLT_CTRL		BIT(8)
75 
76 #define SLT_PLAT_PDN			BIT(8)
77 #define SLT_PLAT_PUP			BIT(9)
78 
79 #define MASTER1_MAPPING			BIT(1)
80 #define MASTER2_MAPPING			BIT(2)
81 
82 #define MIPI_PWR_REQ			BIT(0)
83 #define PCIE_PWR_REQ			BIT(1)
84 #define OTG1_PWR_REQ			BIT(2)
85 #define OTG2_PWR_REQ			BIT(3)
86 #define HSIOMIX_PWR_REQ			BIT(4)
87 #define DDRMIX_PWR_REQ			BIT(5)
88 #define GPU2D_PWR_REQ			BIT(6)
89 #define GPUMIX_PWR_REQ			BIT(7)
90 #define VPUMIX_PWR_REQ			BIT(8)
91 #define GPU3D_PWR_REQ			BIT(9)
92 #define DISPMIX_PWR_REQ			BIT(10)
93 #define VPU_G1_PWR_REQ			BIT(11)
94 #define VPU_G2_PWR_REQ			BIT(12)
95 #define VPU_H1_PWR_REQ			BIT(13)
96 
97 #define DDRMIX_ADB400_SYNC		BIT(2)
98 #define HSIOMIX_ADB400_SYNC		(0x3 << 5)
99 #define DISPMIX_ADB400_SYNC		BIT(7)
100 #define VPUMIX_ADB400_SYNC		BIT(8)
101 #define GPU3D_ADB400_SYNC		BIT(9)
102 #define GPU2D_ADB400_SYNC		BIT(10)
103 #define GPUMIX_ADB400_SYNC		BIT(11)
104 #define DDRMIX_ADB400_ACK		BIT(20)
105 #define HSIOMIX_ADB400_ACK		(0x3 << 23)
106 #define DISPMIX_ADB400_ACK		BIT(25)
107 #define VPUMIX_ADB400_ACK		BIT(26)
108 #define GPU3D_ADB400_ACK		BIT(27)
109 #define GPU2D_ADB400_ACK		BIT(28)
110 #define GPUMIX_ADB400_ACK		BIT(29)
111 
112 #define MIPI_PGC			0xc00
113 #define PCIE_PGC			0xc40
114 #define OTG1_PGC			0xc80
115 #define OTG2_PGC			0xcc0
116 #define HSIOMIX_PGC			0xd00
117 #define DDRMIX_PGC			0xd40
118 #define GPU2D_PGC			0xd80
119 #define GPUMIX_PGC			0xdc0
120 #define VPUMIX_PGC			0xe00
121 #define GPU3D_PGC			0xe40
122 #define DISPMIX_PGC			0xe80
123 #define VPU_G1_PGC			0xec0
124 #define VPU_G2_PGC			0xf00
125 #define VPU_H1_PGC			0xf40
126 
127 #define IRQ_IMR_NUM			U(4)
128 
129 #endif /* GPC_REG_H */
130