| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.cc | 645 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits()); in lslv()
646 VIXL_ASSERT(rd.GetSizeInBits() == rm.GetSizeInBits()); in lslv()
654 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits()); in lsrv()
655 VIXL_ASSERT(rd.GetSizeInBits() == rm.GetSizeInBits()); in lsrv()
663 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits()); in asrv()
664 VIXL_ASSERT(rd.GetSizeInBits() == rm.GetSizeInBits()); in asrv()
672 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits()); in rorv()
673 VIXL_ASSERT(rd.GetSizeInBits() == rm.GetSizeInBits()); in rorv()
683 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits()); in bfm()
685 Emit(SF(rd) | BFM | N | ImmR(immr, rd.GetSizeInBits()) | in bfm()
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| D | macro-assembler-aarch64.cc | 450 unsigned reg_size = rd.GetSizeInBits(); in MoveImmediateHelper()
518 int reg_size = dst.GetSizeInBits(); in OneInstrMoveImmediateHelper()
837 unsigned reg_size = rd.GetSizeInBits(); in LogicalMacro()
918 VIXL_ASSERT(operand.GetRegister().GetSizeInBits() <= rd.GetSizeInBits()); in LogicalMacro()
1643 int reg_size = dst.GetSizeInBits(); in MoveImmediateForShiftedOp()
1695 VIXL_ASSERT(dst.GetSizeInBits() == src.GetSizeInBits()); in Move()
1696 VIXL_ASSERT(dst.GetSizeInBits() <= kXRegSize); in Move()
1697 int operand_size = static_cast<int>(dst.GetSizeInBits()); in Move()
1860 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits()); in AddSubWithCarryMacro()
1881 VIXL_ASSERT(operand.GetRegister().GetSizeInBits() == rd.GetSizeInBits()); in AddSubWithCarryMacro()
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| D | registers-aarch64.h | 137 int GetSizeInBits() const { return DecodeSizeInBits(size_); } in GetSizeInBits() function
358 return GetSizeInBits(); in GetMaxSizeInBytes()
370 return GetSizeInBits(); in GetMinSizeInBytes()
783 VIXL_ASSERT(GetSizeInBits() == SIZE); \
788 VIXL_CONSTEXPR int GetSizeInBits() const { return SIZE; } \
791 return PARENT::IsValid() && (PARENT::GetSizeInBits() == SIZE); \
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| D | operands-aarch64.h | 47 size_(reg1.GetSizeInBits()),
130 VIXL_ASSERT(other.GetSizeInBits() == size_); in Combine()
136 VIXL_ASSERT(other.GetSizeInBits() == size_); in Remove()
966 size_t GetSizeInBits() const { return GetSizeInBytes() * kBitsPerByte; } in GetSizeInBits() function
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| D | assembler-aarch64.h | 763 VIXL_ASSERT(lsb + width <= static_cast<unsigned>(rn.GetSizeInBits())); in bfi()
766 (rd.GetSizeInBits() - lsb) & (rd.GetSizeInBits() - 1), in bfi()
776 VIXL_ASSERT(lsb + width <= static_cast<unsigned>(rn.GetSizeInBits())); in bfxil()
789 VIXL_ASSERT(shift < static_cast<unsigned>(rd.GetSizeInBits())); in asr()
790 sbfm(rd, rn, shift, rd.GetSizeInBits() - 1); in asr()
799 VIXL_ASSERT(lsb + width <= static_cast<unsigned>(rn.GetSizeInBits())); in sbfiz()
802 (rd.GetSizeInBits() - lsb) & (rd.GetSizeInBits() - 1), in sbfiz()
812 VIXL_ASSERT(lsb + width <= static_cast<unsigned>(rn.GetSizeInBits())); in sbfx()
829 unsigned reg_size = rd.GetSizeInBits(); in lsl()
836 VIXL_ASSERT(shift < static_cast<unsigned>(rd.GetSizeInBits())); in lsr()
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| D | operands-aarch64.cc | 435 VIXL_ASSERT(reg.GetSizeInBits() > static_cast<int>(kXRegSize)); in GenericOperand()
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| D | assembler-sve-aarch64.cc | 2200 VIXL_ASSERT(static_cast<unsigned>(rn.GetSizeInBits()) >= in index()
2202 VIXL_ASSERT(static_cast<unsigned>(rm.GetSizeInBits()) >= in index()
2214 VIXL_ASSERT(static_cast<unsigned>(rn.GetSizeInBits()) >= in index()
2226 VIXL_ASSERT(static_cast<unsigned>(rm.GetSizeInBits()) >= in index()
5687 VIXL_ASSERT(static_cast<unsigned>(rn.GetSizeInBits()) >= in cpy()
5702 VIXL_ASSERT(static_cast<unsigned>(vn.GetSizeInBits()) == in cpy()
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| D | simulator-aarch64.h | 258 unsigned GetSizeInBits() const { return size_in_bytes_ * kBitsPerByte; } in GetSizeInBits() function
446 lane < (static_cast<int>(register_.GetSizeInBits() / chunk_size)); in SetAllBits()
768 return register_.GetSizeInBits() / LaneSizeInBitsFromFormat(vform); in LaneCountFromFormat()
1788 VIXL_ASSERT(operand.GetCPURegister().GetSizeInBits() <= 64);
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| D | macro-assembler-aarch64.h | 784 Mov(rd, (rd.GetSizeInBits() == kXRegSize) ? ~imm : (~imm & kWRegMask)); in Mvn()
7126 return AcquireRegisterOfSize(reg.GetSizeInBits()); in AcquireSameSizeAs()
7130 return AcquireVRegisterOfSize(reg.GetSizeInBits()); in AcquireSameSizeAs()
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| D | disasm-aarch64.cc | 9536 switch (reg.GetSizeInBits()) { in AppendRegisterNameToOutput()
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| D | simulator-aarch64.cc | 11588 for (unsigned i = 0; i < pn.GetSizeInBits(); i++) { in VisitSVEFFRWriteFromPredicate()
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| /external/vixl/src/aarch32/ |
| D | instructions-aarch32.h | 122 int GetSizeInBits() const { return (value_ & kSizeMask) >> kSizeShift; } in GetSizeInBits() function
124 return (GetType() == kNoRegister) ? 0 : (GetSizeInBits() / 8); in GetRegSizeInBytes()
126 bool Is64Bits() const { return GetSizeInBits() == 64; } in Is64Bits()
127 bool Is128Bits() const { return GetSizeInBits() == 128; } in Is128Bits()
620 switch (reg.GetSizeInBits()) { in RegisterToList()
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| /external/tensorflow/tensorflow/compiler/xla/service/llvm_ir/ |
| D | llvm_util.h | 135 int GetSizeInBits(llvm::Type* type);
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| D | llvm_util.cc | 216 int GetSizeInBits(llvm::Type* type) { in GetSizeInBits() function
222 bits += GetSizeInBits(element_type); in GetSizeInBits()
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| /external/tensorflow/tensorflow/compiler/xla/service/gpu/ |
| D | ir_emitter.cc | 400 int element_size = llvm_ir::GetSizeInBits(element_type); in EmitAtomicOperationUsingCAS()
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| D | ir_emitter_unnested.cc | 4336 int bit_width = llvm_ir::GetSizeInBits(element_type); in EmitFullWarpShuffleDownLoopForReduce()
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| /external/vixl/test/aarch64/ |
| D | test-disasm-neon-aarch64.cc | 297 v, VRegister((v.GetCode() + 1) % 32, v.GetSizeInBits(), v.GetLanes())
299 VLIST2(v), VRegister((v.GetCode() + 2) % 32, v.GetSizeInBits(), v.GetLanes())
301 VLIST3(v), VRegister((v.GetCode() + 3) % 32, v.GetSizeInBits(), v.GetLanes())
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