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Searched refs:HI (Results 1 – 25 of 681) sorted by relevance

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/external/llvm-project/clang-tools-extra/clangd/unittests/
DHoverTests.cpp41 [](HoverInfo &HI) { in TEST() argument
42 HI.NamespaceScope = ""; in TEST()
43 HI.Name = "foo"; in TEST()
44 HI.Kind = index::SymbolKind::Function; in TEST()
45 HI.Documentation = "Best foo ever."; in TEST()
46 HI.Definition = "void foo()"; in TEST()
47 HI.ReturnType = "void"; in TEST()
48 HI.Type = "void ()"; in TEST()
49 HI.Parameters.emplace(); in TEST()
58 [](HoverInfo &HI) { in TEST() argument
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCMCTargetDesc.h144 #define PPC_REGS_LO_HI(LO, HI) \ argument
149 LO##26, LO##27, LO##28, LO##29, LO##30, LO##31, HI##0, HI##1, HI##2, \
150 HI##3, HI##4, HI##5, HI##6, HI##7, HI##8, HI##9, HI##10, HI##11, \
151 HI##12, HI##13, HI##14, HI##15, HI##16, HI##17, HI##18, HI##19, \
152 HI##20, HI##21, HI##22, HI##23, HI##24, HI##25, HI##26, HI##27, \
153 HI##28, HI##29, HI##30, HI##31 \
/external/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCMCTargetDesc.h146 #define PPC_REGS_LO_HI(LO, HI) \ argument
151 LO##26, LO##27, LO##28, LO##29, LO##30, LO##31, HI##0, HI##1, HI##2, \
152 HI##3, HI##4, HI##5, HI##6, HI##7, HI##8, HI##9, HI##10, HI##11, \
153 HI##12, HI##13, HI##14, HI##15, HI##16, HI##17, HI##18, HI##19, \
154 HI##20, HI##21, HI##22, HI##23, HI##24, HI##25, HI##26, HI##27, \
155 HI##28, HI##29, HI##30, HI##31 \
/external/pcre/dist2/src/sljit/
DsljitNativePPC_common.c136 #define HI(opcode) ((opcode) << 26) macro
139 #define ADD (HI(31) | LO(266))
140 #define ADDC (HI(31) | LO(10))
141 #define ADDE (HI(31) | LO(138))
142 #define ADDI (HI(14))
143 #define ADDIC (HI(13))
144 #define ADDIS (HI(15))
145 #define ADDME (HI(31) | LO(234))
146 #define AND (HI(31) | LO(28))
147 #define ANDI (HI(28))
[all …]
DsljitNativeMIPS_common.c119 #define HI(opcode) ((opcode) << 26) macro
130 #define ABS_S (HI(17) | FMT_S | LO(5))
131 #define ADD_S (HI(17) | FMT_S | LO(0))
132 #define ADDIU (HI(9))
133 #define ADDU (HI(0) | LO(33))
134 #define AND (HI(0) | LO(36))
135 #define ANDI (HI(12))
136 #define B (HI(4))
137 #define BAL (HI(1) | (17 << 16))
139 #define BC1EQZ (HI(17) | (9 << 21) | FT(TMP_FREG3))
[all …]
/external/llvm/test/CodeGen/AArch64/
Dnontemporal.ll16 ; CHECK-NEXT: mov d[[HI:[0-9]+]], v0[1]
17 ; CHECK-NEXT: stnp d0, d[[HI]], [x0]
25 ; CHECK-NEXT: mov d[[HI:[0-9]+]], v0[1]
26 ; CHECK-NEXT: stnp d0, d[[HI]], [x0]
34 ; CHECK-NEXT: mov d[[HI:[0-9]+]], v0[1]
35 ; CHECK-NEXT: stnp d0, d[[HI]], [x0]
43 ; CHECK-NEXT: mov s[[HI:[0-9]+]], v0[1]
44 ; CHECK-NEXT: stnp s0, s[[HI]], [x0]
52 ; CHECK-NEXT: mov s[[HI:[0-9]+]], v0[1]
53 ; CHECK-NEXT: stnp s0, s[[HI]], [x0]
[all …]
/external/llvm-project/clang-tools-extra/clangd/
DHover.cpp307 void fillFunctionTypeAndParams(HoverInfo &HI, const Decl *D, in fillFunctionTypeAndParams() argument
310 HI.Parameters.emplace(); in fillFunctionTypeAndParams()
312 HI.Parameters->emplace_back(toHoverInfoParam(PVD, Policy)); in fillFunctionTypeAndParams()
322 HI.ReturnType = printType(FD->getReturnType(), Policy); in fillFunctionTypeAndParams()
326 HI.Type = printType(QT, Policy); in fillFunctionTypeAndParams()
495 HoverInfo HI; in getHoverContents() local
498 HI.AccessSpecifier = getAccessSpelling(D->getAccess()).str(); in getHoverContents()
499 HI.NamespaceScope = getNamespaceScope(D); in getHoverContents()
500 if (!HI.NamespaceScope->empty()) in getHoverContents()
501 HI.NamespaceScope->append("::"); in getHoverContents()
[all …]
/external/llvm/lib/CodeGen/AsmPrinter/
DDwarfAccelTable.cpp166 for (HashList::const_iterator HI = Buckets[i].begin(), in EmitHashes() local
168 HI != HE; ++HI) { in EmitHashes()
169 uint32_t HashValue = (*HI)->HashValue; in EmitHashes()
186 for (HashList::const_iterator HI = Buckets[i].begin(), in emitOffsets() local
188 HI != HE; ++HI) { in emitOffsets()
189 uint32_t HashValue = (*HI)->HashValue; in emitOffsets()
196 MCSymbolRefExpr::create((*HI)->Sym, Context), in emitOffsets()
209 for (HashList::const_iterator HI = Buckets[i].begin(), in EmitData() local
211 HI != HE; ++HI) { in EmitData()
214 if (PrevHash != UINT64_MAX && PrevHash != (*HI)->HashValue) in EmitData()
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dnontemporal.ll13 ; CHECK-NEXT: mov d[[HI:[0-9]+]], v0[1]
14 ; CHECK-NEXT: stnp d0, d[[HI]], [x0]
22 ; CHECK-NEXT: mov d[[HI:[0-9]+]], v0[1]
23 ; CHECK-NEXT: stnp d0, d[[HI]], [x0]
31 ; CHECK-NEXT: mov d[[HI:[0-9]+]], v0[1]
32 ; CHECK-NEXT: stnp d0, d[[HI]], [x0]
40 ; CHECK-NEXT: mov s[[HI:[0-9]+]], v0[1]
41 ; CHECK-NEXT: stnp s0, s[[HI]], [x0]
49 ; CHECK-NEXT: mov s[[HI:[0-9]+]], v0[1]
50 ; CHECK-NEXT: stnp s0, s[[HI]], [x0]
[all …]
Dmul-lohi.ll6 ; CHECK: umulh [[HI:x[0-9]+]], x0, x2
7 ; CHECK: madd [[TEMP1:x[0-9]+]], x0, x3, [[HI]]
13 ; CHECK-BE: umulh [[HI:x[0-9]+]], x1, x3
14 ; CHECK-BE: madd [[TEMP1:x[0-9]+]], x1, x2, [[HI]]
28 ; CHECK: umulh [[HI:x[0-9]+]], x0, x2
29 ; CHECK-NEXT: madd [[TEMP1:x[0-9]+]], x0, x3, [[HI]]
40 ; CHECK: umulh [[HI:x[0-9]+]], x0, x2
41 ; CHECK-NEXT: madd [[TEMP1:x[0-9]+]], x0, x3, [[HI]]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.raw.tbuffer.load.d16.ll16 ; PREGFX10-UNPACKED: tbuffer_load_format_d16_xy v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-…
17 ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
30 ; PREGFX10-UNPACKED: tbuffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0…
31 ; GFX10-UNPACKED: tbuffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]…
32 ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
34 ; PREGFX10-PACKED: tbuffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9…
35 ; GFX10-PACKED: tbuffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:…
36 ; PACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
45 ; PREGFX10-UNPACKED: tbuffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[…
46 ; GFX10-UNPACKED: tbuffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9…
[all …]
Dzext-i64-bit-operand.ll4 ; GCN: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
7 ; GCN-NOT: v[[HI]]
11 ; GCN-NOT: v[[HI]]
13 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
24 ; GCN: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
27 ; GCN-NOT: v[[HI]]
30 ; GCN-NOT: v[[HI]]
33 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
Dllvm.amdgcn.buffer.load.format.d16.ll14 ; UNPACKED: buffer_load_format_d16_xy v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+…
15 ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
27 ; UNPACKED: buffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]…
28 ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
30 ; PACKED: buffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+}…
31 ; PACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
40 ; UNPACKED: buffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9…
41 ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
43 ; PACKED: buffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+…
44 ; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[HI]]
Dllvm.amdgcn.struct.tbuffer.load.d16.ll18 ; PREGFX10-UNPACKED: tbuffer_load_format_d16_xy v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, [[ZEROREG]],…
19 ; PREGFX10-UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
33 ; PREGFX10-UNPACKED: tbuffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, [[ZEROREG]]…
34 ; PREGFX10-UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
36 ; PREGFX10-PACKED: tbuffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, [[ZEROREG]], …
37 ; GFX10-PACKED: tbuffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, [[ZEROREG]], s[{…
38 ; PACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
48 ; PREGFX10-UNPACKED: tbuffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, [[ZEROREG]…
49 ; PREGFX10-UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
51 ; PREGFX10-PACKED: tbuffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, [[ZEROREG]],…
[all …]
Dstore-hi16.ll2 …einstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GCN,GFX906,GFX9,NO-D16-HI %s
3 …achineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GCN,GFX803,NO-D16-HI %s
11 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
31 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
51 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
70 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
90 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
204 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
205 ; NO-D16-HI-NEXT: flat_store_short v[0:1], v2
222 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
[all …]
Dfract.f64.ll12 ; SI-DAG: v_fract_f64_e32 [[FRC:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
16 ; SI-DAG: v_cmp_class_f64_e64 vcc, v{{\[}}[[LO]]:[[HI]]], 3
18 ; SI: v_cndmask_b32_e32 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], vcc
19 ; SI: v_add_f64 [[SUB0:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]{{\]}}, -v{{\[}}[[RESLO]]:[[RESHI]…
20 ; SI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]{{\]}}, -[[SUB0]]
39 ; SI-DAG: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
43 ; SI-DAG: v_cmp_class_f64_e64 vcc, v{{\[}}[[LO]]:[[HI]]], 3
45 ; SI: v_cndmask_b32_e32 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], vcc
46 ; SI: v_add_f64 [[SUB0:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO]]:[[HI]]{{\]}}, -v{{\[}}[[RESLO]]:[[RESHI…
47 ; SI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO]]:[[HI]]{{\]}}, -[[SUB0]]
[all …]
Dllvm.amdgcn.raw.buffer.load.format.d16.ll14 ; UNPACKED: buffer_load_format_d16_xy v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+…
15 ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
27 ; UNPACKED: buffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]…
28 ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
30 ; PACKED: buffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+}…
39 ; UNPACKED: buffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9…
40 ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
42 ; PACKED: buffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+…
43 ; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[HI]]
Dllvm.amdgcn.tbuffer.load.d16.ll14 ; UNPACKED: tbuffer_load_format_d16_xy v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]…
15 ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
27 ; UNPACKED: tbuffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9…
28 ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
30 ; PACKED: tbuffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+…
31 ; PACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
40 ; UNPACKED: tbuffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-…
41 ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
43 ; PACKED: tbuffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]…
44 ; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[HI]]
Dllvm.amdgcn.struct.buffer.load.format.d16.ll14 ; UNPACKED: buffer_load_format_d16_xy v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, {{v[0-9]+}}, s[{{[0-9]…
15 ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
27 ; UNPACKED: buffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, {{v[0-9]+}}, s[{{[0-9…
28 ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
30 ; PACKED: buffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, {{v[0-9]+}}, s[{{[0-9]+…
31 ; PACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
40 ; UNPACKED: buffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, {{v[0-9]+}}, s[{{[0-…
41 ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
43 ; PACKED: buffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, {{v[0-9]+}}, s[{{[0-9]…
44 ; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[HI]]
/external/llvm/test/CodeGen/AMDGPU/
Dfcanonicalize.ll190 ; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], v[[LO]]{{$}}
191 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
200 ; GCN-DAG: v_bfrev_b32_e32 v[[HI:[0-9]+]], 1{{$}}
201 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
210 ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x3ff00000{{$}}
211 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
220 ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0xbff00000{{$}}
221 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
230 ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x40300000{{$}}
231 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
[all …]
Dzext-i64-bit-operand.ll4 ; GCN: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
7 ; GCN-NOT: v[[HI]]
11 ; GCN-NOT: v[[HI]]
13 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
24 ; GCN: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
27 ; GCN-NOT: v[[HI]]
30 ; GCN-NOT: v[[HI]]
33 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
Dfract.f64.ll12 ; SI-DAG: v_fract_f64_e32 [[FRC:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
16 ; SI-DAG: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
18 ; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]]
19 ; SI: v_add_f64 [[SUB0:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]{{\]}}, -v{{\[}}[[RESLO]]:[[RESHI]…
20 ; SI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]{{\]}}, -[[SUB0]]
39 ; SI-DAG: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
43 ; SI-DAG: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
45 ; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]]
46 ; SI: v_add_f64 [[SUB0:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO]]:[[HI]]{{\]}}, -v{{\[}}[[RESLO]]:[[RESHI…
47 ; SI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO]]:[[HI]]{{\]}}, -[[SUB0]]
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dfp128-bitcast-after-operation.ll16 ; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]])
18 ; PPC64: and [[FLIP_BIT:[0-9]+]], [[HI]], [[MASK_REG]]
19 ; PPC64-DAG: xor 3, [[HI]], [[FLIP_BIT]]
25 ; PPC64-P8-DAG: mfvsrd [[HI:[0-9]+]], 1
28 ; PPC64-P8: and [[FLIP_BIT:[0-9]+]], [[HI]], [[SHIFT_REG]]
29 ; PPC64-P8-DAG: xor 3, [[HI]], [[FLIP_BIT]]
58 ; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]])
61 ; PPC64-DAG: xor 3, [[HI]], [[FLIP_BIT]]
67 ; PPC64-P8-DAG: mfvsrd [[HI:[0-9]+]], 1
71 ; PPC64-P8-DAG: xor 3, [[HI]], [[FLIP_BIT]]
[all …]
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dfp128-bitcast-after-operation.ll12 ; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]])
14 ; PPC64-DAG: rldicr [[FLIP_BIT:[0-9]+]], [[HI]], 0, 0
15 ; PPC64-DAG: xor 3, [[HI]], [[FLIP_BIT]]
21 ; PPC64-P8-DAG: mffprd [[HI:[0-9]+]], 1
22 ; PPC64-P8-DAG: rldicr [[FLIP_BIT:[0-9]+]], [[HI]], 0, 0
23 ; PPC64-P8-DAG: xor 3, [[HI]], [[FLIP_BIT]]
49 ; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]])
52 ; PPC64-DAG: xor 3, [[HI]], [[FLIP_BIT]]
58 ; PPC64-P8-DAG: mffprd [[HI:[0-9]+]], 1
62 ; PPC64-P8-DAG: xor 3, [[HI]], [[FLIP_BIT]]
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Utils/
DARMBaseInfo.h39 HI, // Unsigned higher Greater than, or unordered enumerator
59 case HI: return LS; in getOppositeCondition()
60 case LS: return HI; in getOppositeCondition()
77 case ARMCC::LO: return ARMCC::HI; in getSwappedCondition()
78 case ARMCC::HI: return ARMCC::LO; in getSwappedCondition()
156 case ARMCC::HI: return "hi"; in ARMCondCodeToString()
179 .Case("hi", ARMCC::HI) in ARMCondCodeFromString()

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