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Searched refs:HSLS_IDM_REGS_BASE (Results 1 – 2 of 2) sorted by relevance

/external/arm-trusted-firmware/plat/brcm/board/stingray/include/
Dsr_def.h179 #define HSLS_IDM_REGS_BASE 0x68e00000 macro
322 #define DMAC_M0_IDM_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0x408)
324 #define DMAC_M0_IDM_RESET_CONTROL (HSLS_IDM_REGS_BASE + 0x800)
356 #define PNOR_IDM_BASE (HSLS_IDM_REGS_BASE + 0xb000)
375 #define NAND_IDM_IDM_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0xa408)
376 #define NAND_IDM_IDM_RESET_CONTROL (HSLS_IDM_REGS_BASE + 0xa800)
384 #define SDIO_IDM0_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0x2408)
385 #define SDIO_IDM1_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0x3408)
386 #define SDIO_IDM0_IDM_RESET_CONTROL (HSLS_IDM_REGS_BASE + 0x2800)
397 #define ROM_S0_IDM_IO_STATUS (HSLS_IDM_REGS_BASE + 0x9500)
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/external/arm-trusted-firmware/plat/brcm/board/stingray/src/
Dbl31_setup.c299 #define AMAC_IDM0_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0x4408)
570 #define I2S_RESET_CONTROL (HSLS_IDM_REGS_BASE + 0x1800)
571 #define I2S_IDM_IO_CONTROL (HSLS_IDM_REGS_BASE + 0x1408)