| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURegisterBankInfo.cpp | 683 Register HiLHS = MRI->createGenericVirtualRegister(HalfTy); in split64BitValueForMapping() local
686 MRI->setRegBank(HiLHS, *Bank); in split64BitValueForMapping()
689 Regs.push_back(HiLHS); in split64BitValueForMapping()
693 .addDef(HiLHS) in split64BitValueForMapping()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURegisterBankInfo.cpp | 668 Register HiLHS = MRI->createGenericVirtualRegister(HalfTy); in split64BitValueForMapping() local
671 MRI->setRegBank(HiLHS, *Bank); in split64BitValueForMapping()
674 Regs.push_back(HiLHS); in split64BitValueForMapping()
678 .addDef(HiLHS) in split64BitValueForMapping()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 1373 SDValue LoLHS, HiLHS, LoRHS, HiRHS; in SplitVecRes_OverflowOp() local
1375 GetSplitVector(N->getOperand(0), LoLHS, HiLHS); in SplitVecRes_OverflowOp()
1378 std::tie(LoLHS, HiLHS) = DAG.SplitVectorOperand(N, 0); in SplitVecRes_OverflowOp()
1386 SDNode *HiNode = DAG.getNode(Opcode, dl, HiVTs, HiLHS, HiRHS).getNode(); in SplitVecRes_OverflowOp()
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| D | TargetLowering.cpp | 7533 SDValue HiLHS; in expandMULO() local
7539 HiLHS = in expandMULO()
7548 HiLHS = DAG.getConstant(0, dl, VT); in expandMULO()
7565 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS }; in expandMULO()
7568 SDValue Args[] = { HiLHS, LHS, HiRHS, RHS }; in expandMULO()
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 1477 SDValue LoLHS, HiLHS, LoRHS, HiRHS; in SplitVecRes_OverflowOp() local
1479 GetSplitVector(N->getOperand(0), LoLHS, HiLHS); in SplitVecRes_OverflowOp()
1482 std::tie(LoLHS, HiLHS) = DAG.SplitVectorOperand(N, 0); in SplitVecRes_OverflowOp()
1490 SDNode *HiNode = DAG.getNode(Opcode, dl, HiVTs, HiLHS, HiRHS).getNode(); in SplitVecRes_OverflowOp()
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| D | TargetLowering.cpp | 8025 SDValue HiLHS; in expandMULO() local
8031 HiLHS = in expandMULO()
8040 HiLHS = DAG.getConstant(0, dl, VT); in expandMULO()
8057 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS }; in expandMULO()
8060 SDValue Args[] = { HiLHS, LHS, HiRHS, RHS }; in expandMULO()
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| /external/llvm-project/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 2956 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt); in LowerUMULO_SMULO() local
2958 SDValue Args[] = { HiLHS, LHS, HiRHS, RHS }; in LowerUMULO_SMULO()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 2975 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt); in LowerUMULO_SMULO() local
2977 SDValue Args[] = { HiLHS, LHS, HiRHS, RHS }; in LowerUMULO_SMULO()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 2950 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt); in LowerUMULO_SMULO() local
2952 SDValue Args[] = { HiLHS, LHS, HiRHS, RHS }; in LowerUMULO_SMULO()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 3421 SDValue HiLHS = in ExpandNode() local
3434 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS }; in ExpandNode()
|