| /external/capstone/ |
| D | MathExtras.h | 37 static inline uint32_t Hi_32(uint64_t Value) { in Hi_32() function
161 uint32_t Hi = Hi_32(Value); in CountLeadingZeros_64()
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| /external/llvm-project/llvm/lib/Target/VE/ |
| D | VEFrameLowering.cpp | 263 .addImm(Hi_32(NumBytes)); in emitSPAdjustment()
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| D | VEInstrInfo.td | 60 return CurDAG->getTargetConstant(Hi_32(N->getZExtValue()),
77 return CurDAG->getTargetConstant(Hi_32(getFpImmVal(N)), SDLoc(N), MVT::i32);
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| /external/llvm/include/llvm/Support/ |
| D | MathExtras.h | 248 inline uint32_t Hi_32(uint64_t Value) {
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| /external/llvm-project/llvm/lib/Support/ |
| D | APInt.cpp | 1410 borrow = Hi_32(p) - Hi_32(subres); in KnuthDiv()
1517 U[i * 2 + 1] = Hi_32(tmp); in divide()
1526 V[i * 2 + 1] = Hi_32(tmp); in divide()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Support/ |
| D | APInt.cpp | 1411 borrow = Hi_32(p) - Hi_32(subres); in KnuthDiv()
1518 U[i * 2 + 1] = Hi_32(tmp); in divide()
1527 V[i * 2 + 1] = Hi_32(tmp); in divide()
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| /external/swiftshader/third_party/llvm-subzero/include/llvm/Support/ |
| D | MathExtras.h | 248 constexpr inline uint32_t Hi_32(uint64_t Value) {
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/ |
| D | MathExtras.h | 320 constexpr inline uint32_t Hi_32(uint64_t Value) {
|
| /external/llvm-project/llvm/include/llvm/Support/ |
| D | MathExtras.h | 349 constexpr inline uint32_t Hi_32(uint64_t Value) {
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 2305 if (Lo_32(Val) != 0 && Hi_32(Val) != 0 && !RHS->hasOneUse()) { in performAndCombine()
2318 SDValue HiRHS = DAG.getConstant(Hi_32(Val), SL, MVT::i32); in performAndCombine()
2585 DAG.getConstant(Hi_32(CVal), SL, MVT::i32)); in PerformDAGCombine()
2594 DAG.getConstant(Hi_32(CVal), SL, MVT::i32)); in PerformDAGCombine()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonGenInsert.cpp | 681 return isInt<8>(Lo_32(V)) && isInt<8>(Hi_32(V)); in isSmallConstant()
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| D | HexagonBitSimplify.cpp | 1427 unsigned Lo = Lo_32(C), Hi = Hi_32(C); in genTfrConst()
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonGenInsert.cpp | 681 return isInt<8>(Lo_32(V)) && isInt<8>(Hi_32(V)); in isSmallConstant()
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| D | HexagonBitSimplify.cpp | 1431 unsigned Lo = Lo_32(C), Hi = Hi_32(C); in genTfrConst()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonGenInsert.cpp | 633 return isInt<8>(Lo_32(V)) && isInt<8>(Hi_32(V)); in isSmallConstant()
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| D | HexagonBitSimplify.cpp | 1384 unsigned Lo = Lo_32(C), Hi = Hi_32(C); in genTfrConst()
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| /external/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3343 if ((Hi_32(ImmOp64) & 0x7ff00000) == 0) { in convertIntToDoubleImm()
3447 if (loadImmediate(Hi_32(ImmOp64), FirstReg, Mips::NoRegister, true, false, in expandLoadDoubleImmToGPR()
3514 !((Hi_32(ImmOp64) & 0xffff0000) && (Hi_32(ImmOp64) & 0x0000ffff))) { in expandLoadDoubleImmToFPR()
3525 loadImmediate(Hi_32(ImmOp64), TmpReg, Mips::NoRegister, true, false, in expandLoadDoubleImmToFPR()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3315 if ((Hi_32(ImmOp64) & 0x7ff00000) == 0) { in convertIntToDoubleImm()
3419 if (loadImmediate(Hi_32(ImmOp64), FirstReg, Mips::NoRegister, true, false, in expandLoadDoubleImmToGPR()
3486 !((Hi_32(ImmOp64) & 0xffff0000) && (Hi_32(ImmOp64) & 0x0000ffff))) { in expandLoadDoubleImmToFPR()
3497 loadImmediate(Hi_32(ImmOp64), TmpReg, Mips::NoRegister, true, false, in expandLoadDoubleImmToFPR()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1562 int s8 = Hi_32(Value); in processInstruction()
|
| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1787 int s8 = Hi_32(Value); in processInstruction()
|
| /external/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1574 int s8 = Hi_32(Value); in processInstruction()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 3919 return buildRSRC(B, MRI, 0, Hi_32(DefaultFormat), BasePtr); in buildAddr64RSrc()
3928 return buildRSRC(B, MRI, -1, Hi_32(DefaultFormat), BasePtr); in buildOffsetSrc()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Support/Windows/ |
| D | Path.inc | 812 Hi_32(Size),
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| /external/llvm-project/llvm/lib/Support/Windows/ |
| D | Path.inc | 832 Hi_32(Size),
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 3953 DAG.getConstant(Hi_32(CVal), SL, MVT::i32)); in PerformDAGCombine()
3964 DAG.getConstant(Hi_32(CVal), SL, MVT::i32)); in PerformDAGCombine()
|