/external/llvm-project/llvm/test/CodeGen/X86/ |
D | select-mmx.ll | 3 ; RUN: llc -mtriple=i686-unknown-unknown -mattr=+mmx < %s | FileCheck %s --check-prefix=I32 30 ; I32-LABEL: test47: 31 ; I32: # %bb.0: 32 ; I32-NEXT: pushl %ebp 33 ; I32-NEXT: .cfi_def_cfa_offset 8 34 ; I32-NEXT: .cfi_offset %ebp, -8 35 ; I32-NEXT: movl %esp, %ebp 36 ; I32-NEXT: .cfi_def_cfa_register %ebp 37 ; I32-NEXT: andl $-8, %esp 38 ; I32-NEXT: subl $8, %esp [all …]
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/external/llvm/lib/Target/WebAssembly/ |
D | WebAssemblyInstrMemory.td | 61 def LOAD_I32 : I<(outs I32:$dst), (ins i32imm:$off, I32:$addr, 64 def LOAD_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr, 67 def LOAD_F32 : I<(outs F32:$dst), (ins i32imm:$off, I32:$addr, 70 def LOAD_F64 : I<(outs F64:$dst), (ins i32imm:$off, I32:$addr, 77 def : Pat<(i32 (load I32:$addr)), (LOAD_I32 0, $addr, 0)>; 78 def : Pat<(i64 (load I32:$addr)), (LOAD_I64 0, $addr, 0)>; 79 def : Pat<(f32 (load I32:$addr)), (LOAD_F32 0, $addr, 0)>; 80 def : Pat<(f64 (load I32:$addr)), (LOAD_F64 0, $addr, 0)>; 83 def : Pat<(i32 (load (regPlusImm I32:$addr, imm:$off))), 85 def : Pat<(i64 (load (regPlusImm I32:$addr, imm:$off))), [all …]
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D | WebAssemblyInstrInteger.td | 59 def EQZ_I32 : I<(outs I32:$dst), (ins I32:$src), 60 [(set I32:$dst, (setcc I32:$src, 0, SETEQ))], 62 def EQZ_I64 : I<(outs I32:$dst), (ins I64:$src), 63 [(set I32:$dst, (setcc I64:$src, 0, SETEQ))], 69 def : Pat<(rotl I32:$lhs, (and I32:$rhs, 31)), (ROTL_I32 I32:$lhs, I32:$rhs)>; 70 def : Pat<(rotr I32:$lhs, (and I32:$rhs, 31)), (ROTR_I32 I32:$lhs, I32:$rhs)>; 76 def SELECT_I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs, I32:$cond), 77 [(set I32:$dst, (select I32:$cond, I32:$lhs, I32:$rhs))], 79 def SELECT_I64 : I<(outs I64:$dst), (ins I64:$lhs, I64:$rhs, I32:$cond), 80 [(set I64:$dst, (select I32:$cond, I64:$lhs, I64:$rhs))], [all …]
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D | WebAssemblyInstrFormats.td | 33 def _I32 : I<(outs I32:$dst), (ins I32:$src), 34 [(set I32:$dst, (node I32:$src))], 41 def _I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs), 42 [(set I32:$dst, (node I32:$lhs, I32:$rhs))], 65 def _I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs), 66 [(set I32:$dst, (setcc I32:$lhs, I32:$rhs, cond))], 68 def _I64 : I<(outs I32:$dst), (ins I64:$lhs, I64:$rhs), 69 [(set I32:$dst, (setcc I64:$lhs, I64:$rhs, cond))], 73 def _F32 : I<(outs I32:$dst), (ins F32:$lhs, F32:$rhs), 74 [(set I32:$dst, (setcc F32:$lhs, F32:$rhs, cond))], [all …]
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D | WebAssemblyInstrConv.td | 18 def I32_WRAP_I64 : I<(outs I32:$dst), (ins I64:$src), 19 [(set I32:$dst, (trunc I64:$src))], 22 def I64_EXTEND_S_I32 : I<(outs I64:$dst), (ins I32:$src), 23 [(set I64:$dst, (sext I32:$src))], 25 def I64_EXTEND_U_I32 : I<(outs I64:$dst), (ins I32:$src), 26 [(set I64:$dst, (zext I32:$src))], 34 def : Pat<(i64 (anyext I32:$src)), (I64_EXTEND_U_I32 I32:$src)>; 40 def I32_TRUNC_S_F32 : I<(outs I32:$dst), (ins F32:$src), 41 [(set I32:$dst, (fp_to_sint F32:$src))], 43 def I32_TRUNC_U_F32 : I<(outs I32:$dst), (ins F32:$src), [all …]
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
D | WebAssemblyInstrInteger.td | 16 defm _I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins), 17 [(set I32:$dst, (node I32:$src))], 27 defm _I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs), (outs), (ins), 28 [(set I32:$dst, (node I32:$lhs, I32:$rhs))], 37 defm _I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs), (outs), (ins), 38 [(set I32:$dst, (setcc I32:$lhs, I32:$rhs, cond))], 41 defm _I64 : I<(outs I32:$dst), (ins I64:$lhs, I64:$rhs), (outs), (ins), 42 [(set I32:$dst, (setcc I64:$lhs, I64:$rhs, cond))], 89 defm EQZ_I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins), 90 [(set I32:$dst, (setcc I32:$src, 0, SETEQ))], [all …]
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D | WebAssemblyInstrBulkMemory.td | 39 (ins i32imm_op:$seg, i32imm_op:$idx, I32:$dest, 40 I32:$offset, I32:$size), 42 [(int_wasm_memory_init (i32 timm:$seg), (i32 timm:$idx), I32:$dest, 43 I32:$offset, I32:$size 57 I32:$dst, I32:$src, I32:$len), 60 I32:$dst, I32:$src, I32:$len 67 BULK_I<(outs), (ins i32imm_op:$idx, I32:$dst, I32:$value, I32:$size), 69 [(wasm_memset (i32 imm:$idx), I32:$dst, I32:$value, I32:$size)],
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D | WebAssemblyInstrConv.td | 15 defm I32_WRAP_I64 : I<(outs I32:$dst), (ins I64:$src), (outs), (ins), 16 [(set I32:$dst, (trunc I64:$src))], 19 defm I64_EXTEND_S_I32 : I<(outs I64:$dst), (ins I32:$src), (outs), (ins), 20 [(set I64:$dst, (sext I32:$src))], 23 defm I64_EXTEND_U_I32 : I<(outs I64:$dst), (ins I32:$src), (outs), (ins), 24 [(set I64:$dst, (zext I32:$src))], 29 defm I32_EXTEND8_S_I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins), 30 [(set I32:$dst, (sext_inreg I32:$src, i8))], 33 defm I32_EXTEND16_S_I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins), 34 [(set I32:$dst, (sext_inreg I32:$src, i16))], [all …]
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/external/llvm-project/llvm/lib/Target/WebAssembly/ |
D | WebAssemblyInstrInteger.td | 16 defm _I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins), 17 [(set I32:$dst, (node I32:$src))], 27 defm _I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs), (outs), (ins), 28 [(set I32:$dst, (node I32:$lhs, I32:$rhs))], 37 defm _I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs), (outs), (ins), 38 [(set I32:$dst, (setcc I32:$lhs, I32:$rhs, cond))], 41 defm _I64 : I<(outs I32:$dst), (ins I64:$lhs, I64:$rhs), (outs), (ins), 42 [(set I32:$dst, (setcc I64:$lhs, I64:$rhs, cond))], 89 defm EQZ_I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins), 90 [(set I32:$dst, (setcc I32:$src, 0, SETEQ))], [all …]
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D | WebAssemblyInstrConv.td | 15 defm I32_WRAP_I64 : I<(outs I32:$dst), (ins I64:$src), (outs), (ins), 16 [(set I32:$dst, (trunc I64:$src))], 19 defm I64_EXTEND_S_I32 : I<(outs I64:$dst), (ins I32:$src), (outs), (ins), 20 [(set I64:$dst, (sext I32:$src))], 23 defm I64_EXTEND_U_I32 : I<(outs I64:$dst), (ins I32:$src), (outs), (ins), 24 [(set I64:$dst, (zext I32:$src))], 29 defm I32_EXTEND8_S_I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins), 30 [(set I32:$dst, (sext_inreg I32:$src, i8))], 33 defm I32_EXTEND16_S_I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins), 34 [(set I32:$dst, (sext_inreg I32:$src, i16))], [all …]
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D | WebAssemblyInstrTable.td | 23 defm TABLE_SET_#rt : I<(outs), (ins table32_op:$table, rt:$val, I32:$i), 30 defm TABLE_GROW_#rt : I<(outs I32:$sz), (ins table32_op:$table, I32:$n, rt:$val), 37 defm TABLE_FILL_#rt : I<(outs), (ins table32_op:$table, I32:$n, rt:$val, I32:$i), 49 defm TABLE_SIZE : I<(outs I32:$sz), (ins table32_op:$table), 58 defm TABLE_COPY : I<(outs), (ins table32_op:$table1, table32_op:$table2, I32:$n, I32:$s, I32:$d),
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/external/skia/src/core/ |
D | SkVM.h | 482 struct I32 { struct 606 void assert_true(I32 cond, I32 debug); 607 void assert_true(I32 cond, F32 debug) { assert_true(cond, pun_to_I32(debug)); } in assert_true() 608 void assert_true(I32 cond) { assert_true(cond, cond); } in assert_true() 611 void store8 (Ptr ptr, I32 val); 612 void store16 (Ptr ptr, I32 val); 613 void store32 (Ptr ptr, I32 val); 615 void store64 (Ptr ptr, I32 lo, I32 hi); // *ptr = lo|(hi<<32) 616 void store128(Ptr ptr, I32 x, I32 y, I32 z, I32 w); // *ptr = x|(y<<32)|(z<<64)|(w<<96) 619 I32 index(); [all …]
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/external/llvm-project/llvm/lib/Target/Hexagon/ |
D | HexagonPatterns.td | 441 def: OpR_R_pat<F2_conv_w2sf, pf1<sint_to_fp>, f32, I32>; 443 def: OpR_R_pat<F2_conv_w2df, pf1<sint_to_fp>, f64, I32>; 446 def: OpR_R_pat<F2_conv_uw2sf, pf1<uint_to_fp>, f32, I32>; 448 def: OpR_R_pat<F2_conv_uw2df, pf1<uint_to_fp>, f64, I32>; 462 def: Pat<(i32 (bitconvert F32:$v)), (I32:$v)>; 463 def: Pat<(f32 (bitconvert I32:$v)), (F32:$v)>; 484 def: Pat<(sext_inreg I32:$Rs, i8), (A2_sxtb I32:$Rs)>; 485 def: Pat<(sext_inreg I32:$Rs, i16), (A2_sxth I32:$Rs)>; 490 def: Pat<(i64 (sext I32:$Rs)), (A2_sxtw I32:$Rs)>; 491 def: Pat<(Zext64 I32:$Rs), (ToZext64 $Rs)>; [all …]
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D | HexagonIntrinsics.td | 12 : Pat <(IntID I32:$Rs), 13 (MI I32:$Rs)>; 16 : Pat <(IntID I32:$Rs, I32:$Rt), 17 (MI I32:$Rs, I32:$Rt)>; 20 : Pat <(IntID I32:$Rs, I64:$Rt), 21 (MI I32:$Rs, I64:$Rt)>; 82 def : Pat <(int_hexagon_A2_not I32:$Rs), 83 (A2_subri -1, I32:$Rs)>; 86 def : Pat <(int_hexagon_A2_neg I32:$Rs), 87 (A2_subri 0, I32:$Rs)>; [all …]
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D | HexagonPatternsHVX.td | 100 def: Pat<(ResType (Load I32:$Rt)), 101 (MI I32:$Rt, 0)>; 102 def: Pat<(ResType (Load (add I32:$Rt, ImmPred:$s))), 103 (MI I32:$Rt, imm:$s)>; 116 def: Pat<(ResType (Load (valignaddr I32:$Rt))), 117 (MI I32:$Rt, 0)>; 118 def: Pat<(ResType (Load (add (valignaddr I32:$Rt), ImmPred:$Off))), 119 (MI I32:$Rt, imm:$Off)>; 142 def: Pat<(Store Value:$Vs, I32:$Rt), 143 (MI I32:$Rt, 0, Value:$Vs)>; [all …]
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
D | HexagonPatterns.td | 411 def: OpR_R_pat<F2_conv_w2sf, pf1<sint_to_fp>, f32, I32>; 413 def: OpR_R_pat<F2_conv_w2df, pf1<sint_to_fp>, f64, I32>; 416 def: OpR_R_pat<F2_conv_uw2sf, pf1<uint_to_fp>, f32, I32>; 418 def: OpR_R_pat<F2_conv_uw2df, pf1<uint_to_fp>, f64, I32>; 432 def: Pat<(i32 (bitconvert F32:$v)), (I32:$v)>; 433 def: Pat<(f32 (bitconvert I32:$v)), (F32:$v)>; 454 def: Pat<(sext_inreg I32:$Rs, i8), (A2_sxtb I32:$Rs)>; 455 def: Pat<(sext_inreg I32:$Rs, i16), (A2_sxth I32:$Rs)>; 460 def: Pat<(i64 (sext I32:$Rs)), (A2_sxtw I32:$Rs)>; 461 def: Pat<(Zext64 I32:$Rs), (ToZext64 $Rs)>; [all …]
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D | HexagonIntrinsics.td | 12 : Pat <(IntID I32:$Rs), 13 (MI I32:$Rs)>; 16 : Pat <(IntID I32:$Rs, I32:$Rt), 17 (MI I32:$Rs, I32:$Rt)>; 20 : Pat <(IntID I32:$Rs, I64:$Rt), 21 (MI I32:$Rs, I64:$Rt)>; 82 def : Pat <(int_hexagon_A2_not I32:$Rs), 83 (A2_subri -1, I32:$Rs)>; 86 def : Pat <(int_hexagon_A2_neg I32:$Rs), 87 (A2_subri 0, I32:$Rs)>; [all …]
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D | HexagonPatternsHVX.td | 99 def: Pat<(ResType (Load I32:$Rt)), 100 (MI I32:$Rt, 0)>; 101 def: Pat<(ResType (Load (add I32:$Rt, ImmPred:$s))), 102 (MI I32:$Rt, imm:$s)>; 115 def: Pat<(ResType (Load (valignaddr I32:$Rt))), 116 (MI I32:$Rt, 0)>; 117 def: Pat<(ResType (Load (add (valignaddr I32:$Rt), ImmPred:$Off))), 118 (MI I32:$Rt, imm:$Off)>; 141 def: Pat<(Store Value:$Vs, I32:$Rt), 142 (MI I32:$Rt, 0, Value:$Vs)>; [all …]
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonIntrinsics.td | 21 : Pat <(IntID I32:$Rs), 22 (MI I32:$Rs)>; 34 : Pat<(IntID I32:$Rs, ImmPred:$It), 35 (MI I32:$Rs, ImmPred:$It)>; 39 : Pat<(IntID ImmPred:$Is, I32:$Rt), 40 (MI ImmPred:$Is, I32:$Rt)>; 47 : Pat<(IntID I32:$Rs, I64:$Rt), 48 (MI I32:$Rs, I64:$Rt)>; 51 : Pat <(IntID I32:$Rs, I32:$Rt), 52 (MI I32:$Rs, I32:$Rt)>; [all …]
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/external/libxaac/decoder/armv7/ |
D | ixheaacd_dec_DCT2_64_asm.s | 97 VSUB.I32 Q11, Q3, Q1 99 VADD.I32 Q10, Q3, Q1 101 VSUB.I32 Q9, Q0, Q2 103 VADD.I32 Q8, Q0, Q2 127 VADD.I32 Q13, Q8, Q15 129 VADD.I32 Q12, Q11, Q14 133 VSUB.I32 Q7, Q14, Q11 136 VSUB.I32 Q6, Q8, Q15 144 VSUB.I32 Q11, Q3, Q1 146 VADD.I32 Q10, Q3, Q1 [all …]
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D | ixheaacd_dct3_32.s | 66 VADD.I32 Q2, Q1, Q0 82 VSUB.I32 Q5, Q3, Q4 104 VADD.I32 Q2, Q1, Q0 126 VSUB.I32 Q5, Q3, Q4 159 VADD.I32 Q2, Q1, Q0 167 VSUB.I32 Q5, Q3, Q4 204 VADD.I32 Q2, Q1, Q0 218 VSUB.I32 Q5, Q3, Q4 244 VSUB.I32 D2, D2, D4 288 VADD.I32 D14, D11, D28 [all …]
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D | ixheaacd_post_twiddle.s | 131 VADD.I32 Q14, Q14, Q13 132 VSUB.I32 Q15, Q15, Q12 163 VADD.I32 Q11, Q11, Q8 166 VSUB.I32 Q10, Q9, Q10 188 VADD.I32 Q7, Q15, Q1 189 VADD.I32 Q13, Q14, Q0 202 VADD.I32 Q12, Q10, Q2 210 VADD.I32 Q8, Q11, Q8 238 VADD.I32 Q14, Q14, Q13 239 VSUB.I32 Q15, Q15, Q12 [all …]
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/external/llvm-project/mlir/test/lib/Dialect/Test/ |
D | TestOps.td | 57 let results = (outs TupleOf<[I32, F32]>); 61 let results = (outs NestedTupleOf<[I32, F32]>); 88 TensorRankOf<[I8, I32, F32], [0, 1]>:$arg0 193 let results = (outs I32:$val); 204 let results = (outs I32:$val); 215 let results = (outs I32:$val); 389 And<[ElementTypeIsPred<"x", I32>, 540 Variadic<I32>:$a, 541 Variadic<I32>:$b, 542 I32:$c, [all …]
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/external/llvm-project/polly/test/GPGPU/ |
D | spir-typesize.ll | 9 ; RUN: FileCheck -check-prefix=I32 %s 15 ; I32: target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-i128:128:… 16 ; I32-NEXT: target triple = "spir-unknown-unknown" 18 ; I32-LABEL: define spir_kernel void @FUNC_double_parallel_loop_SCOP_0_KERNEL_0(i8 addrspace(1)* %M… 19 ; I32-NEXT: entry: 20 ; I32-NEXT: %0 = call i32 @__gen_ocl_get_group_id0() 21 ; I32-NEXT: %__gen_ocl_get_group_id0 = zext i32 %0 to i64 22 ; I32-NEXT: %1 = call i32 @__gen_ocl_get_group_id1() 23 ; I32-NEXT: %__gen_ocl_get_group_id1 = zext i32 %1 to i64 24 ; I32-NEXT: %2 = call i32 @__gen_ocl_get_local_id0() [all …]
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/external/rust/crates/hashlink/tests/ |
D | serde.rs | 25 Token::I32(10), in map_serde_tokens() 27 Token::I32(20), in map_serde_tokens() 29 Token::I32(30), in map_serde_tokens() 53 Token::I32(10), in set_serde_tokens() 54 Token::I32(20), in set_serde_tokens() 55 Token::I32(30), in set_serde_tokens()
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