| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | callbr-asm-outputs-pred-succ.ll | 6 ; The block containting the INLINEASM_BR should have a fallthrough and its
12 ; The fallthrough is a block containing a second INLINEASM_BR. Check it has two successors,
18 ; Check the second INLINEASM_BR target block is preceded by the block with the
19 ; second INLINEASM_BR.
23 ; Check the first INLINEASM_BR target block is predecessed by the block with
24 ; the first INLINEASM_BR.
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| D | tail-dup-asm-goto.ll | 4 ; Ensure that we don't duplicate a block with an "INLINEASM_BR" instruction
31 …; CHECK: INLINEASM_BR &"#$0 $1 $2", 9 /* sideeffect mayload attdialect */, 13 /* imm */, 42, 13 …
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| D | shrinkwrap-callbr.ll | 4 ;; Ensure that shrink-wrapping understands that INLINEASM_BR may exit
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 87 case ISD::INLINEASM_BR: break; in numberRCValPredInSU()
124 case ISD::INLINEASM_BR: break; in numberRCValSuccInSU()
450 case ISD::INLINEASM_BR: in SUSchedulingCost()
553 case ISD::INLINEASM_BR: in initNumRegDefsLeft()
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| D | InstrEmitter.cpp | 1046 case ISD::INLINEASM_BR: { in EmitSpecialNode()
1052 unsigned TgtOpc = Node->getOpcode() == ISD::INLINEASM_BR in EmitSpecialNode()
1053 ? TargetOpcode::INLINEASM_BR in EmitSpecialNode()
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| D | ScheduleDAGFast.cpp | 483 Node->getOpcode() == ISD::INLINEASM_BR) { in DelayForLiveRegsBottomUp()
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 91 case ISD::INLINEASM_BR: break; in numberRCValPredInSU()
128 case ISD::INLINEASM_BR: break; in numberRCValSuccInSU()
454 case ISD::INLINEASM_BR: in SUSchedulingCost()
557 case ISD::INLINEASM_BR: in initNumRegDefsLeft()
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| D | InstrEmitter.cpp | 1143 case ISD::INLINEASM_BR: { in EmitSpecialNode()
1149 unsigned TgtOpc = Node->getOpcode() == ISD::INLINEASM_BR in EmitSpecialNode()
1150 ? TargetOpcode::INLINEASM_BR in EmitSpecialNode()
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| D | ScheduleDAGFast.cpp | 483 Node->getOpcode() == ISD::INLINEASM_BR) { in DelayForLiveRegsBottomUp()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | PHIEliminationUtils.cpp | 55 I->getOpcode() == TargetOpcode::INLINEASM_BR) { in findPHICopyInsertPoint()
|
| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | ifcvt-size.mir | 515 # The INLINEASM_BR instructions aren't analyzable, but they are identical so we
525 # CHECK-NEXT: INLINEASM_BR
543 INLINEASM_BR &"b ${0:l}", 1, 13, blockaddress(@fn9, %ir-block.lab1)
553 INLINEASM_BR &"b ${0:l}", 1, 13, blockaddress(@fn9, %ir-block.lab1)
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 728 INLINEASM_BR, enumerator
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 905 INLINEASM_BR, enumerator
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.cpp | 311 case TargetOpcode::INLINEASM_BR: { in getInstSizeInBytes()
|
| /external/llvm-project/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.cpp | 299 case TargetOpcode::INLINEASM_BR: { in getInstSizeInBytes()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonMachineScheduler.cpp | 115 case TargetOpcode::INLINEASM_BR: in isResourceAvailable()
171 case TargetOpcode::INLINEASM_BR: in reserveResources()
|
| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonMachineScheduler.cpp | 115 case TargetOpcode::INLINEASM_BR: in isResourceAvailable()
171 case TargetOpcode::INLINEASM_BR: in reserveResources()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 332 case ISD::INLINEASM_BR: { in Select()
|
| /external/llvm-project/llvm/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 332 case ISD::INLINEASM_BR: { in Select()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRInstrInfo.cpp | 491 case TargetOpcode::INLINEASM_BR: { in getInstSizeInBytes()
|
| /external/llvm-project/llvm/lib/Target/AVR/ |
| D | AVRInstrInfo.cpp | 491 case TargetOpcode::INLINEASM_BR: { in getInstSizeInBytes()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 581 case TargetOpcode::INLINEASM_BR: { // Inline Asm: Variable size. in getInstSizeInBytes()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfo.cpp | 483 case TargetOpcode::INLINEASM_BR: { in getInstSizeInBytes()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCVSXSwapRemoval.cpp | 425 case PPC::INLINEASM_BR: in gatherVectorInstructions()
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 582 case TargetOpcode::INLINEASM_BR: { // Inline Asm: Variable size. in getInstSizeInBytes()
|