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Searched refs:INSTR (Results 1 – 25 of 27) sorted by relevance

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/external/mesa3d/src/freedreno/ir2/
Ddisasm-a2xx.c129 #define INSTR(opc, num_srcs) [opc] = { num_srcs, #opc } macro
130 INSTR(ADDv, 2),
131 INSTR(MULv, 2),
132 INSTR(MAXv, 2),
133 INSTR(MINv, 2),
134 INSTR(SETEv, 2),
135 INSTR(SETGTv, 2),
136 INSTR(SETGTEv, 2),
137 INSTR(SETNEv, 2),
138 INSTR(FRACv, 1),
[all …]
/external/llvm-project/llvm/test/MC/RISCV/
Drv32-relaxation.s2 # RUN: | llvm-objdump -d -M no-aliases - | FileCheck --check-prefix=INSTR %s
4 # RUN: | llvm-objdump -d -M no-aliases - | FileCheck --check-prefix=RELAX-INSTR %s
21 #INSTR: c.bnez a0, 0x91e
22 #RELAX-INSTR: c.bnez a0, 0
25 #INSTR: c.bnez a0, 0x8d4
26 #RELAX-INSTR: c.bnez a0, 0
29 #INSTR-NEXT: bne a0, zero, 0xa20
30 #RELAX-INSTR-NEXT: bne a0, zero, 0
33 #INSTR-NEXT: bne a0, zero, 0x7d2
34 #RELAX-INSTR-NEXT: bne a0, zero, 0
[all …]
Drv64-relaxation.s2 # RUN: | llvm-objdump -d -M no-aliases - | FileCheck --check-prefix=INSTR %s
4 # RUN: | llvm-objdump -d -M no-aliases - | FileCheck --check-prefix=RELAX-INSTR %s
21 #INSTR: c.bnez a0, 0x90e
22 #RELAX-INSTR: c.bnez a0, 0
25 #INSTR: c.bnez a0, 0x8d4
26 #RELAX-INSTR: c.bnez a0, 0
29 #INSTR-NEXT: bne a0, zero, 0xa10
30 #RELAX-INSTR-NEXT: bne a0, zero, 0
33 #INSTR-NEXT: bne a0, zero, 0x7d2
34 #RELAX-INSTR-NEXT: bne a0, zero, 0
[all …]
Dfunction-call.s2 # RUN: | llvm-objdump -d - | FileCheck --check-prefix=INSTR %s
12 # INSTR: auipc ra, 0
13 # INSTR: jalr ra
17 # INSTR: auipc ra, 0
18 # INSTR: jalr ra
25 # INSTR: auipc ra, 0
26 # INSTR: jalr ra
31 # INSTR: auipc ra, 0
32 # INSTR: jalr ra
37 # INSTR: auipc ra, 0
[all …]
Dtail-call.s2 # RUN: | llvm-objdump -d - | FileCheck --check-prefix=INSTR %s
9 # RUN: | llvm-objdump -d - | FileCheck --check-prefix=INSTR %s
19 # INSTR: auipc t1, 0
20 # INSTR: jr t1
24 # INSTR: auipc t1, 0
25 # INSTR: jr t1
33 # INSTR: auipc t1, 0
34 # INSTR: jr t1
39 # INSTR: auipc t1, 0
40 # INSTR: jr t1
[all …]
Dfixups.s5 # RUN: | FileCheck -check-prefix=CHECK-INSTR %s
15 # CHECK-INSTR: lui t1, 74565
19 # CHECK-INSTR: lw a0, 1656(t1)
22 # CHECK-INSTR: addi a1, t1, 1656
25 # CHECK-INSTR: sw a0, 1656(t1)
30 # CHECK-INSTR: auipc t1, 0
33 # CHECK-INSTR: addi t1, t1, -16
36 # CHECK-INSTR: sw t1, -16(t1)
40 # CHECK-INSTR: jal zero, 0x0
43 # CHECK-INSTR: jal zero, 0x50d14
[all …]
Drelocations.s2 # RUN: | FileCheck -check-prefix=INSTR -check-prefix=FIXUP %s
9 # INSTR - Check the instruction is handled properly by the ASMPrinter
19 # INSTR: lui t1, %hi(foo)
24 # INSTR: lui t1, %hi(foo+4)
29 # INSTR: lui t1, %tprel_hi(foo)
34 # INSTR: lui t1, %tprel_hi(foo+4)
39 # INSTR: addi t1, t1, %lo(foo)
44 # INSTR: addi t1, t1, %lo(foo+4)
49 # INSTR: addi t1, t1, %tprel_lo(foo)
54 # INSTR: addi t1, t1, %tprel_lo(foo+4)
[all …]
Dpseudo-jump.s2 # RUN: | llvm-objdump -d - | FileCheck --check-prefix=INSTR %s
12 # INSTR: auipc t6, 0
13 # INSTR: jr t6
20 # INSTR: auipc ra, 0
21 # INSTR: ret
26 # INSTR: auipc t6, 0
27 # INSTR: jr t6
Drv64-relax-all.s1 …attr=+c %s | llvm-objdump -d -M no-aliases --no-show-raw-insn - | FileCheck %s --check-prefix=INSTR
3 …-all | llvm-objdump -d -M no-aliases --no-show-raw-insn - | FileCheck %s --check-prefix=RELAX-INSTR
9 # INSTR: c.beqz a0, 0x0 <NEAR>
10 # RELAX-INSTR: beq a0, zero, 0x0 <NEAR>
13 # INSTR: c.j 0x0 <NEAR>
14 # RELAX-INSTR: jal zero, 0x0 <NEAR>
Dfixups-compressed.s4 # RUN: | llvm-objdump -d -M no-aliases - | FileCheck --check-prefix=CHECK-INSTR %s
10 # CHECK-INSTR: c.j 0
13 # CHECK-INSTR: c.jal 0x8
16 # CHECK-INSTR: c.beqz a3, 0x0
19 # CHECK-INSTR: c.bnez a5, 0x0
Dhilo-constaddr-expr.s4 # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-INSTR
20 # CHECK-INSTR: lui t0, 48
21 # CHECK-INSTR: lw ra, 292(t0)
28 # CHECK-INSTR: lui t1, 0
29 # CHECK-INSTR: lw sp, -8(t1)
Dcompressed-relocations.s2 # RUN: | FileCheck -check-prefix=INSTR -check-prefix=FIXUP %s
11 # INSTR - Check the instruction is handled properly by the ASMPrinter
15 # INSTR: c.jal foo
21 # INSTR: c.bnez a0, foo
Dhilo-constaddr.s2 # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-INSTR
14 # CHECK-INSTR: lui t0, 912092
15 # CHECK-INSTR: lw ra, -273(t0)
/external/llvm/test/MC/Mips/
Dhilo-addressing.s5 # RUN: | llvm-objdump -disassemble - | FileCheck %s -check-prefix=CHECK-INSTR
29 # CHECK-INSTR: lui $4, 3
30 # CHECK-INSTR: addiu $4, $4, 292
35 # CHECK-INSTR: lui $5, 0
36 # CHECK-INSTR: lw $5, -8($5)
/external/llvm-project/llvm/test/MC/Mips/
Dhilo-addressing.s5 # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-INSTR
29 # CHECK-INSTR: lui $4, 3
30 # CHECK-INSTR: addiu $4, $4, 292
35 # CHECK-INSTR: lui $5, 0
36 # CHECK-INSTR: lw $5, -8($5)
/external/mesa3d/src/gallium/drivers/etnaviv/
Detnaviv_compiler_tgsi.c1788 #define INSTR(n, f, ...) \ macro
1791 INSTR(MOV, trans_instr, .opc = INST_OPCODE_MOV, .src = {2, -1, -1}),
1792 INSTR(RCP, trans_instr, .opc = INST_OPCODE_RCP, .src = {2, -1, -1}),
1793 INSTR(RSQ, trans_instr, .opc = INST_OPCODE_RSQ, .src = {2, -1, -1}),
1794 INSTR(MUL, trans_instr, .opc = INST_OPCODE_MUL, .src = {0, 1, -1}),
1795 INSTR(ADD, trans_instr, .opc = INST_OPCODE_ADD, .src = {0, 2, -1}),
1796 INSTR(DP2, trans_instr, .opc = INST_OPCODE_DP2, .src = {0, 1, -1}),
1797 INSTR(DP3, trans_instr, .opc = INST_OPCODE_DP3, .src = {0, 1, -1}),
1798 INSTR(DP4, trans_instr, .opc = INST_OPCODE_DP4, .src = {0, 1, -1}),
1799 INSTR(DST, trans_instr, .opc = INST_OPCODE_DST, .src = {0, 1, -1}),
[all …]
/external/perfetto/src/trace_processor/metrics/android/
Dandroid_proxy_power.sql49 SELECT SUBSTR(str_value, INSTR(str_value, '/') + 1)
54 SELECT SUBSTR(str, 0, INSTR(str, '/'))
Dandroid_sysui_cuj.sql275 TRIM(SUBSTR(remainder, INSTR(remainder, ",") + 1)) AS remainder
/external/llvm-project/llvm/test/TableGen/
Ddag-isel-res-order.td15 // CHECK: OPC_EmitNode2, TARGET_VAL(::INSTR)
18 def INSTR : Instruction {
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dppc-passname.ll2 …oop-instr-form-prep -o /dev/null 2>&1 | FileCheck %s -check-prefix=STOP-BEFORE-LOOP-INSTR-FORM-PREP
3 ; STOP-BEFORE-LOOP-INSTR-FORM-PREP-NOT: -ppc-loop-instr-form-prep
4 ; STOP-BEFORE-LOOP-INSTR-FORM-PREP-NOT: "ppc-loop-instr-form-prep" pass is not registered.
5 ; STOP-BEFORE-LOOP-INSTR-FORM-PREP-NOT: Prepare loop for ppc preferred instruction forms
7 …loop-instr-form-prep -o /dev/null 2>&1 | FileCheck %s -check-prefix=STOP-AFTER-LOOP-INSTR-FORM-PREP
8 ; STOP-AFTER-LOOP-INSTR-FORM-PREP: -ppc-loop-instr-form-prep
9 ; STOP-AFTER-LOOP-INSTR-FORM-PREP-NOT: "ppc-loop-instr-form-prep" pass is not registered.
10 ; STOP-AFTER-LOOP-INSTR-FORM-PREP: Prepare loop for ppc preferred instruction forms
/external/mesa3d/src/freedreno/.gitlab-ci/reference/
Dcrash.log7507 00002320 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0x119 | FORMAT = 0 | SWAP = WZYX }
7509 00000000 VFD_DECODE[0x1].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = 0 | SWAP = WZYX }
7511 00002400 VFD_DECODE[0x2].INSTR: { IDX = 0 | OFFSET = 0x120 | FORMAT = 0 | SWAP = WZYX }
7513 00008040 VFD_DECODE[0x3].INSTR: { IDX = 0 | OFFSET = 0x402 | FORMAT = 0 | SWAP = WZYX }
7515 00000180 VFD_DECODE[0x4].INSTR: { IDX = 0 | OFFSET = 0xc | FORMAT = 0 | SWAP = WZYX }
7517 00002800 VFD_DECODE[0x5].INSTR: { IDX = 0 | OFFSET = 0x140 | FORMAT = 0 | SWAP = WZYX }
7519 00000040 VFD_DECODE[0x6].INSTR: { IDX = 0 | OFFSET = 0x2 | FORMAT = 0 | SWAP = WZYX }
7521 00008a00 VFD_DECODE[0x7].INSTR: { IDX = 0 | OFFSET = 0x450 | FORMAT = 0 | SWAP = WZYX }
7523 00018910 VFD_DECODE[0x8].INSTR: { IDX = 16 | OFFSET = 0xc48 | FORMAT = 0 | SWAP = WZYX }
7525 00000200 VFD_DECODE[0x9].INSTR: { IDX = 0 | OFFSET = 0x10 | FORMAT = 0 | SWAP = WZYX }
[all …]
DdEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log1116 t4 write VFD_DECODE[0].INSTR (a090)
1117 …VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_32_FLOAT | SWAP = WZYX | UNK3…
1120 t4 write VFD_DEST_CNTL[0].INSTR (a0d0)
1121 VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0xf | REGID = r0.x }
1123 t4 write VFD_DECODE[0x1].INSTR (a092)
1124 …VFD_DECODE[0x1].INSTR: { IDX = 0 | OFFSET = 0x10 | FORMAT = FMT6_32_32_32_32_FLOAT | SWAP = WZYX |…
1127 t4 write VFD_DEST_CNTL[0x1].INSTR (a0d1)
1128 VFD_DEST_CNTL[0x1].INSTR: { WRITEMASK = 0xf | REGID = r1.x }
1130 t4 write VFD_DECODE[0x2].INSTR (a094)
1131 … VFD_DECODE[0x2].INSTR: { IDX = 0 | OFFSET = 0x20 | FORMAT = FMT6_32_SINT | SWAP = WZYX | UNK30 }
[all …]
Dglxgears-a420.log546 t0 write VFD_DECODE[0].INSTR (228a)
547 …VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.x …
759 !+ 2c0000df VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | …
1184 t0 write VFD_DECODE[0].INSTR (228a)
1185 …VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z …
1299 !+ 2c0020df VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | …
1766 t0 write VFD_DECODE[0].INSTR (228a)
1767 …VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z …
1775 t0 write VFD_DECODE[0x1].INSTR (228b)
1776 …VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r1.…
[all …]
/external/llvm-project/polly/test/Isl/CodeGen/
Ddead_invariant_load_instruction_referenced_by_parameter_2.ll13 %INSTR = alloca [32 x i32], align 16
29 %arrayidx16 = getelementptr inbounds [32 x i32], [32 x i32]* %INSTR, i64 0, i64 6
33 %arrayidx20 = getelementptr inbounds [32 x i32], [32 x i32]* %INSTR, i64 0, i64 7
/external/webp/src/dsp/
Dmsa_macro.h72 #define MSA_LOAD_FUNC(TYPE, INSTR, FUNC_NAME) \ argument
77 "" #INSTR " %[val_m], %[psrc_m] \n\t" \
85 #define MSA_STORE_FUNC(TYPE, INSTR, FUNC_NAME) \ argument
90 " " #INSTR " %[val_m], %[pdst_m] \n\t" \

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