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/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dlegalize-fdiv.mir30 …; SI: [[INT2:%[0-9]+]]:_(s32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.sca…
39 …TRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](s32), [[FMA1]](s32), [[FMA3]](s32), [[INT3]](s1)
119 …; SI: [[INT2:%[0-9]+]]:_(s32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.sca…
128 …TRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](s32), [[FMA1]](s32), [[FMA3]](s32), [[INT3]](s1)
136 …; VI: [[INT2:%[0-9]+]]:_(s32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.sca…
145 …TRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](s32), [[FMA1]](s32), [[FMA3]](s32), [[INT3]](s1)
153 …; GFX9: [[INT2:%[0-9]+]]:_(s32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.s…
162 …TRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](s32), [[FMA1]](s32), [[FMA3]](s32), [[INT3]](s1)
176 …; GFX10: [[INT2:%[0-9]+]]:_(s32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.…
185 …TRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](s32), [[FMA1]](s32), [[FMA3]](s32), [[INT3]](s1)
[all …]
Dlegalize-fcos.mir123 ; SI: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](s32)
124 ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INT1]](s32), [[INT3]](s32)
135 ; VI: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](s32)
136 ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INT1]](s32), [[INT3]](s32)
168 ; SI: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](s32)
172 …; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[INT1]](s32), [[INT3]](s32), [[INT5]…
183 ; VI: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](s32)
187 …; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[INT1]](s32), [[INT3]](s32), [[INT5]…
221 ; SI: [[INT3:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](s64)
222 ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[INT1]](s64), [[INT3]](s64)
[all …]
Dlegalize-fsin.mir123 ; SI: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](s32)
124 ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INT1]](s32), [[INT3]](s32)
135 ; VI: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](s32)
136 ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INT1]](s32), [[INT3]](s32)
168 ; SI: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](s32)
172 …; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[INT1]](s32), [[INT3]](s32), [[INT5]…
183 ; VI: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](s32)
187 …; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[INT1]](s32), [[INT3]](s32), [[INT5]…
221 ; SI: [[INT3:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](s64)
222 ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[INT1]](s64), [[INT3]](s64)
[all …]
Dlegalize-fptosi.mir337 ; SI: [[INT3:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s64)
338 ; SI: [[FMINNUM_IEEE1:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[INT3]], [[C10]]
Dlegalize-fptoui.mir337 ; SI: [[INT3:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s64)
338 ; SI: [[FMINNUM_IEEE1:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[INT3]], [[C10]]
Dregbankselect-amdgcn.s.buffer.load.ll159 …; CHECK: [[INT3:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY8…
160 ; CHECK: $sgpr3 = COPY [[INT3]](s32)
195 …; GREEDY: [[INT3:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY…
196 ; GREEDY: $sgpr3 = COPY [[INT3]](s32)
236 …; CHECK: [[INT3:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY8…
237 ; CHECK: $sgpr3 = COPY [[INT3]](s32)
296 …; GREEDY: [[INT3:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY…
297 ; GREEDY: $sgpr3 = COPY [[INT3]](s32)
/external/jackson-databind/src/test/java/com/fasterxml/jackson/databind/util/
DArrayBuildersTest.java73 final int[] INT3 = new int[] { 3, 4, 5 }; in testArrayComparator() local
74 Object comp = ArrayBuilders.getArrayComparator(INT3); in testArrayComparator()
76 assertTrue(comp.equals(INT3)); in testArrayComparator()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86AvoidTrailingCall.cpp102 TII.get(X86::INT3)); in runOnMachineFunction()
DX86InstrSystem.td36 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", [(int_x86_int (i8 3))]>;
41 //def : InstAlias<"int\t$3", (INT3)>;
62 (INT3)>, Requires<[NotPS4]>;
DX86ScheduleAtom.td855 def : InstRW<[AtomWrite01_130], (instrs INT3)>;
/external/llvm-project/llvm/lib/Target/X86/
DX86AvoidTrailingCall.cpp129 BuildMI(MBB, MBBI, DL, TII.get(X86::INT3)); in runOnMachineFunction()
DX86InstrSystem.td49 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", [(int_x86_int (i8 3))]>;
55 //def : InstAlias<"int\t$3", (INT3)>;
76 (INT3)>, Requires<[NotPS4]>;
DX86ScheduleAtom.td858 def : InstRW<[AtomWrite01_130], (instrs INT3)>;
/external/antlr/runtime/ObjC/Framework/examples/treerewrite/
DTreeRewriteParser.m322 CommonToken *INT3 = nil;
334 INT3=(CommonToken *)[self match:input TokenType:INT Follow:FOLLOW_INT_in_subrule53];
336 (CommonTree *)[[treeAdaptor create:INT3] retain]
/external/mesa3d/src/gallium/drivers/swr/rasterizer/jitter/
Dbuilder_misc.h196 Value* INT3() in INT3() function
/external/oss-fuzz/projects/mysql-server/targets/
Dfuzz_initfile.dict253 INT3="INT3"
Dfuzz_docommand.dict253 INT3="INT3"
/external/llvm-project/lldb/test/Shell/SymbolFile/DWARF/
Ddwp.s12 # CHECK: (INT3) A = 3
/external/llvm/lib/Target/X86/
DX86InstrSystem.td37 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
43 //def : InstAlias<"int\t$3", (INT3)>;
66 (INT3)>, Requires<[NotPS4]>;
/external/llvm/test/MC/X86/
Dx86-64.s194 INT3 label
/external/llvm-project/llvm/test/MC/X86/
Dx86-64.s199 INT3 label
/external/pcre/dist2/src/sljit/
DsljitNativeX86_common.c196 #define INT3 0xcc macro
954 *inst = INT3; in sljit_emit_op0()
/external/mesa3d/src/mesa/x86/
Dassyntax.h464 #define INT3 CHOICE(int CONST(3), int3, int CONST(3)) macro
1183 #define INT3 int3 macro
/external/capstone/arch/X86/
DX86GenAsmWriter1_reduce.inc583 2616U, // INT3
2301 0U, // INT3
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenSubtargetInfo.inc6388 {DBGFIELD("INT3") 1, false, false, 18, 1, 13, 1, 0, 0}, // #699
7765 {DBGFIELD("INT3") 1, false, false, 96, 2, 2, 1, 0, 0}, // #699
9142 {DBGFIELD("INT3") 1, false, false, 714, 2, 2, 1, 0, 0}, // #699
10519 {DBGFIELD("INT3") 1, false, false, 1, 1, 2, 1, 0, 0}, // #699
11896 {DBGFIELD("INT3") 1, false, false, 714, 2, 2, 1, 0, 0}, // #699
13273 {DBGFIELD("INT3") 1, false, false, 709, 2, 2, 1, 0, 0}, // #699
14650 {DBGFIELD("INT3") 1, false, false, 714, 2, 2, 1, 0, 0}, // #699
16027 {DBGFIELD("INT3") 1, false, false, 3805, 2, 2, 1, 0, 0}, // #699
17404 {DBGFIELD("INT3") 1, false, false, 714, 2, 2, 1, 0, 0}, // #699
18781 {DBGFIELD("INT3") 1, false, false, 0, 0, 2, 1, 0, 0}, // #699
[all …]

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