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Searched refs:INTEL_MASK (Results 1 – 11 of 11) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_defines.h37 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low)) macro
46 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
261 #define BRW_SURFACE_FORMAT_MASK INTEL_MASK(26, 18)
267 #define BRW_SURFACE_TYPE_MASK INTEL_MASK(31, 29)
288 #define GEN8_SURFACE_MOCS_MASK INTEL_MASK(30, 24)
290 #define GEN8_SURFACE_QPITCH_MASK INTEL_MASK(14, 0)
294 #define BRW_SURFACE_HEIGHT_MASK INTEL_MASK(31, 19)
296 #define BRW_SURFACE_WIDTH_MASK INTEL_MASK(18, 6)
298 #define BRW_SURFACE_LOD_MASK INTEL_MASK(5, 2)
300 #define GEN7_SURFACE_HEIGHT_MASK INTEL_MASK(29, 16)
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/external/igt-gpu-tools/assembler/
Dbrw_defines.h32 #define INTEL_MASK(high, low) (((1<<((high)-(low)+1))-1)<<(low)) macro
441 #define BRW_SURFACE_FORMAT_MASK INTEL_MASK(26, 18)
447 #define BRW_SURFACE_TYPE_MASK INTEL_MASK(31, 29)
468 #define BRW_SURFACE_HEIGHT_MASK INTEL_MASK(31, 19)
470 #define BRW_SURFACE_WIDTH_MASK INTEL_MASK(18, 6)
472 #define BRW_SURFACE_LOD_MASK INTEL_MASK(5, 2)
474 #define GEN7_SURFACE_HEIGHT_MASK INTEL_MASK(29, 16)
476 #define GEN7_SURFACE_WIDTH_MASK INTEL_MASK(13, 0)
480 #define BRW_SURFACE_DEPTH_MASK INTEL_MASK(31, 21)
482 #define BRW_SURFACE_PITCH_MASK INTEL_MASK(19, 3)
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/external/mesa3d/src/intel/perf/
Dgen_perf_regs.h27 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low)) macro
32 #define GEN7_RPSTAT1_CURR_GT_FREQ_MASK INTEL_MASK(13, 7)
34 #define GEN7_RPSTAT1_PREV_GT_FREQ_MASK INTEL_MASK(6, 0)
38 #define GEN9_RPSTAT0_CURR_GT_FREQ_MASK INTEL_MASK(31, 23)
40 #define GEN9_RPSTAT0_PREV_GT_FREQ_MASK INTEL_MASK(8, 0)
/external/mesa3d/src/intel/compiler/
Dbrw_nir.h191 #define BRW_NIR_FRAG_OUTPUT_INDEX_MASK INTEL_MASK(0, 0)
193 #define BRW_NIR_FRAG_OUTPUT_LOCATION_MASK INTEL_MASK(31, 1)
Dbrw_eu_defines.h42 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low)) macro
54 assert((fieldval & ~INTEL_MASK(high, low)) == 0); \
55 fieldval & INTEL_MASK(high, low); \
58 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
Dbrw_vec4_generator.cpp755 const int mask = ivb ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17); in generate_tcs_get_instance_id()
1075 brw_imm_ud(ivb ? INTEL_MASK(15, 12) : INTEL_MASK(16, 13))); in generate_tcs_create_barrier_header()
Dbrw_fs_generator.cpp1577 brw_imm_ud(INTEL_MASK(3, 0))); in generate_scratch_header()
1586 brw_imm_ud(INTEL_MASK(31, 10))); in generate_scratch_header()
Dbrw_fs.cpp5028 brw_imm_ud(INTEL_MASK(31, 5))); in lower_sampler_logical_send_gen7()
5049 brw_imm_ud(INTEL_MASK(31, 5))); in lower_sampler_logical_send_gen7()
8121 devinfo->gen >= 11 ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17); in set_tcs_invocation_id()
Dbrw_fs_nir.cpp2772 brw_imm_ud(INTEL_MASK(16, 13))); in nir_emit_tcs_intrinsic()
2778 brw_imm_ud(INTEL_MASK(30, 24))); in nir_emit_tcs_intrinsic()
Dbrw_eu_emit.c2733 (devinfo->gen >= 12 || (ex_desc.ud & INTEL_MASK(15, 12)) == 0)) { in brw_send_indirect_split_message()
/external/igt-gpu-tools/lib/
Dgen7_render.h8 #define INTEL_MASK(high, low) (((1 << ((high) - (low) + 1)) - 1) << (low)) macro