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Searched refs:ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB (Results 1 – 5 of 5) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_surface_formats.c175 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x5] = ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB, in brw_isl_format_for_mesa_format()
/external/mesa3d/prebuilt-intermediates/isl/
Disl_format_layout.c4610 [ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB] = {
4611 .format = ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB,
5832 case ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB: in isl_format_srgb_to_linear()
5833 return ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB; in isl_format_srgb_to_linear()
/external/mesa3d/src/intel/isl/
Disl.h334 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB = 529, enumerator
Disl_format.c647 [PIPE_FORMAT_ASTC_6x5_SRGB] = ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB, in isl_format_for_pipe_format()
/external/mesa3d/src/intel/vulkan/
Danv_formats.c295 fmt1(VK_FORMAT_ASTC_6x5_SRGB_BLOCK, ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB),