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Searched refs:ISL_FORMAT_R8_UNORM (Results 1 – 11 of 11) sorted by relevance

/external/mesa3d/src/intel/vulkan/
Danv_formats.c155 fmt1(VK_FORMAT_R8_UNORM, ISL_FORMAT_R8_UNORM),
347 y_plane(0, ISL_FORMAT_R8_UNORM, RGBA, _ISL_SWIZZLE(GREEN, ZERO, ZERO, ZERO), 1, 1),
348 chroma_plane(1, ISL_FORMAT_R8_UNORM, RGBA, _ISL_SWIZZLE(BLUE, ZERO, ZERO, ZERO), 2, 2),
349 chroma_plane(2, ISL_FORMAT_R8_UNORM, RGBA, _ISL_SWIZZLE(RED, ZERO, ZERO, ZERO), 2, 2)),
351 y_plane(0, ISL_FORMAT_R8_UNORM, RGBA, _ISL_SWIZZLE(GREEN, ZERO, ZERO, ZERO), 1, 1),
354 y_plane(0, ISL_FORMAT_R8_UNORM, RGBA, _ISL_SWIZZLE(GREEN, ZERO, ZERO, ZERO), 1, 1),
355 chroma_plane(1, ISL_FORMAT_R8_UNORM, RGBA, _ISL_SWIZZLE(BLUE, ZERO, ZERO, ZERO), 2, 1),
356 chroma_plane(2, ISL_FORMAT_R8_UNORM, RGBA, _ISL_SWIZZLE(RED, ZERO, ZERO, ZERO), 2, 1)),
358 y_plane(0, ISL_FORMAT_R8_UNORM, RGBA, _ISL_SWIZZLE(GREEN, ZERO, ZERO, ZERO), 1, 1),
361 y_plane(0, ISL_FORMAT_R8_UNORM, RGBA, _ISL_SWIZZLE(GREEN, ZERO, ZERO, ZERO), 1, 1),
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/external/mesa3d/src/intel/isl/
Disl_storage_image.c70 case ISL_FORMAT_R8_UNORM: in isl_is_storage_image_format()
191 case ISL_FORMAT_R8_UNORM: in isl_lower_storage_image_format()
Disl_format.c443 [PIPE_FORMAT_R8_UNORM] = ISL_FORMAT_R8_UNORM, in isl_format_for_pipe_format()
499 [PIPE_FORMAT_I8_UNORM] = ISL_FORMAT_R8_UNORM, in isl_format_for_pipe_format()
513 [PIPE_FORMAT_L8_UNORM] = ISL_FORMAT_R8_UNORM, in isl_format_for_pipe_format()
529 [PIPE_FORMAT_A8_UNORM] = ISL_FORMAT_R8_UNORM, in isl_format_for_pipe_format()
935 format1 = ISL_FORMAT_R8_UNORM; in isl_formats_are_ccs_e_compatible()
938 format2 = ISL_FORMAT_R8_UNORM; in isl_formats_are_ccs_e_compatible()
Disl.h243 ISL_FORMAT_R8_UNORM = 320, enumerator
Disl.c2994 case ISL_FORMAT_R8_UNORM: return 0xA; in isl_format_get_aux_map_encoding()
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_surface_formats.c60 [MESA_FORMAT_R_UNORM8] = ISL_FORMAT_R8_UNORM, in brw_isl_format_for_mesa_format()
262 render = ISL_FORMAT_R8_UNORM; in intel_screen_init_surface_formats()
Dbrw_draw_upload.c188 ISL_FORMAT_R8_UNORM,
Dbrw_wm_surface_state.c550 format = ISL_FORMAT_R8_UNORM; in brw_update_texture_surface()
/external/mesa3d/src/intel/blorp/
Dblorp_blit.c1729 return ISL_FORMAT_R8_UNORM; in get_red_format_for_rgb_format()
2074 params->dst.view.format = ISL_FORMAT_R8_UNORM; in try_blorp_blit()
2348 src_format = ISL_FORMAT_R8_UNORM; in blorp_blit()
2349 dst_format = ISL_FORMAT_R8_UNORM; in blorp_blit()
2567 case ISL_FORMAT_R8_UNORM: in get_ccs_compatible_copy_format()
Dblorp_clear.c401 format = ISL_FORMAT_R8_UNORM; in blorp_clear()
/external/mesa3d/prebuilt-intermediates/isl/
Disl_format_layout.c2750 [ISL_FORMAT_R8_UNORM] = {
2751 .format = ISL_FORMAT_R8_UNORM,