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Searched refs:ISL_SURF_USAGE_STENCIL_BIT (Results 1 – 12 of 12) sorted by relevance

/external/mesa3d/src/intel/isl/
Disl.h906 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2) macro
1913 return usage & ISL_SURF_USAGE_STENCIL_BIT; in isl_surf_usage_is_stencil()
1920 (usage & ISL_SURF_USAGE_STENCIL_BIT); in isl_surf_usage_is_depth_and_stencil()
1926 return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT); in isl_surf_usage_is_depth_or_stencil()
DREADME29 `ISL_SURF_USAGE_STENCIL_BIT`.
Disl.c1599 if ((surf_info->usage & ISL_SURF_USAGE_STENCIL_BIT) && in isl_calc_row_pitch()
2292 assert((info->stencil_surf->usage & ISL_SURF_USAGE_STENCIL_BIT)); in isl_emit_depth_stencil_hiz_s()
2762 bool has_stencil = surf->usage & ISL_SURF_USAGE_STENCIL_BIT; in isl_surf_get_depth_format()
/external/mesa3d/src/intel/blorp/
Dblorp_blit.c1466 } else if (key->dst_usage == ISL_SURF_USAGE_STENCIL_BIT) { in brw_blorp_build_nir_shader()
1824 } else if (params->dst.surf.usage & ISL_SURF_USAGE_STENCIL_BIT) { in try_blorp_blit()
1827 wm_prog_key->dst_usage = ISL_SURF_USAGE_STENCIL_BIT; in try_blorp_blit()
1919 wm_prog_key->dst_usage != ISL_SURF_USAGE_STENCIL_BIT) { in try_blorp_blit()
2139 } else if (wm_prog_key->dst_usage == ISL_SURF_USAGE_STENCIL_BIT) { in try_blorp_blit()
2339 if (src_surf->surf->usage & ISL_SURF_USAGE_STENCIL_BIT) in blorp_blit()
2341 if (dst_surf->surf->usage & ISL_SURF_USAGE_STENCIL_BIT) in blorp_blit()
2344 if (dst_surf->surf->usage & ISL_SURF_USAGE_STENCIL_BIT) { in blorp_blit()
2345 assert(src_surf->surf->usage & ISL_SURF_USAGE_STENCIL_BIT); in blorp_blit()
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_misc_state.c420 view.usage |= ISL_SURF_USAGE_STENCIL_BIT; in brw_emit_depthbuffer()
Dintel_mipmap_tree.c402 mt->surf.usage & (ISL_SURF_USAGE_STENCIL_BIT | ISL_SURF_USAGE_DEPTH_BIT); in make_surface()
460 return ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT | in mt_surf_usage()
463 return ISL_SURF_USAGE_STENCIL_BIT | ISL_SURF_USAGE_TEXTURE_BIT; in mt_surf_usage()
/external/mesa3d/src/gallium/drivers/iris/
Diris_blit.c329 ISL_SURF_USAGE_STENCIL_BIT)) { in iris_resource_blorp_write_aux_usage()
Diris_resource.c541 ISL_SURF_USAGE_STENCIL_BIT : ISL_SURF_USAGE_DEPTH_BIT; in iris_resource_configure_main()
Diris_state.c2570 ISL_SURF_USAGE_STENCIL_BIT)) in iris_create_surface()
3159 view.usage |= ISL_SURF_USAGE_STENCIL_BIT; in iris_set_framebuffer_state()
/external/mesa3d/src/intel/vulkan/
Danv_image.c68 isl_usage |= ISL_SURF_USAGE_STENCIL_BIT; in choose_isl_surf_usage()
Danv_blorp.c1593 (src_surf.surf->usage & ISL_SURF_USAGE_STENCIL_BIT) || in anv_image_msaa_resolve()
DgenX_cmd_buffer.c5149 ISL_SURF_USAGE_STENCIL_BIT); in cmd_buffer_emit_depth_stencil()