Home
last modified time | relevance | path

Searched refs:ISL_TILING_LINEAR_BIT (Results 1 – 9 of 9) sorted by relevance

/external/mesa3d/src/intel/isl/
Disl_gen4.c46 *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT | ISL_TILING_Y0_BIT); in isl_gen4_filter_tiling()
62 ISL_TILING_Y0_BIT : (ISL_TILING_Y0_BIT | ISL_TILING_LINEAR_BIT); in isl_gen4_filter_tiling()
82 *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT); in isl_gen4_filter_tiling()
Disl_gen7.c255 *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT | in isl_gen6_filter_tiling()
261 *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT | in isl_gen6_filter_tiling()
265 *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT); in isl_gen6_filter_tiling()
331 *flags &= ISL_TILING_LINEAR_BIT; in isl_gen6_filter_tiling()
Disl.h487 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR) macro
497 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
/external/mesa3d/src/intel/vulkan/
Danv_image.c111 flags = ISL_TILING_LINEAR_BIT; in choose_isl_tiling_flags()
122 isl_tiling_flags_t legacy_mask = ISL_TILING_LINEAR_BIT; in choose_isl_tiling_flags()
188 *inout_primary_tiling_flags = ISL_TILING_LINEAR_BIT; in anv_image_plane_needs_shadow_surface()
993 isl_tiling_flags = ISL_TILING_LINEAR_BIT; in resolve_ahw_image()
Danv_android.c480 anv_info.isl_tiling_flags = ISL_TILING_LINEAR_BIT; in anv_image_from_gralloc()
Danv_blorp.c179 .tiling_flags = ISL_TILING_LINEAR_BIT); in get_blorp_surf_for_anv_buffer()
/external/mesa3d/src/gallium/drivers/iris/
Diris_resource.c504 tiling_flags = ISL_TILING_LINEAR_BIT; in iris_resource_configure_main()
507 ISL_TILING_X_BIT : ISL_TILING_LINEAR_BIT; in iris_resource_configure_main()
/external/mesa3d/src/mesa/drivers/dri/i965/
Dintel_mipmap_tree.c2673 ISL_TILING_LINEAR_BIT, in intel_miptree_map_blit()
/external/mesa3d/src/intel/blorp/
Dblorp_blit.c2863 .tiling_flags = ISL_TILING_LINEAR_BIT); in do_buffer_copy()