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Searched refs:ISL_TILING_Y0 (Results 1 – 15 of 15) sorted by relevance

/external/mesa3d/src/intel/isl/
Disl_drm.c43 case ISL_TILING_Y0: in isl_tiling_to_i915_tiling()
69 return ISL_TILING_Y0; in isl_tiling_from_i915_tiling()
89 .tiling = ISL_TILING_Y0,
94 .tiling = ISL_TILING_Y0,
101 .tiling = ISL_TILING_Y0,
108 .tiling = ISL_TILING_Y0,
Disl_gen7.c417 if (tiling == ISL_TILING_Y0 && in isl_gen7_choose_image_alignment_el()
Disl_storage_image.c283 case ISL_TILING_Y0: in isl_surf_fill_image_param()
Disl_surface_state.c72 [ISL_TILING_Y0] = YMAJOR,
498 s.TileWalk = info->surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR : in isl_genX()
Disl.c321 assert(tiling == ISL_TILING_X || tiling == ISL_TILING_Y0); in isl_tiling_get_info()
340 case ISL_TILING_Y0: in isl_tiling_get_info()
550 CHOOSE(ISL_TILING_Y0); in isl_surf_choose_tiling()
736 assert(tiling == ISL_TILING_Y0); in isl_choose_image_alignment_el()
2034 if (surf->tiling != ISL_TILING_Y0) in isl_surf_supports_ccs()
2156 } else if (surf->tiling == ISL_TILING_Y0) { in isl_surf_get_ccs_surf()
Disl_emit_depth_stencil.c120 db.TileWalk = info->depth_surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR : in isl_genX()
Disl.h474 ISL_TILING_Y0, /**< Legacy Y tiling */ enumerator
490 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
Disl_tiled_memcpy.c851 } else if (tiling == ISL_TILING_Y0) { in intel_linear_to_tiled()
942 } else if (tiling == ISL_TILING_Y0) { in intel_tiled_to_linear()
/external/mesa3d/src/mesa/drivers/dri/i965/
Dintel_blit.c263 bool dst_y_tiled = dst_tiling == ISL_TILING_Y0; in emit_copy_blit()
264 bool src_y_tiled = src_tiling == ISL_TILING_Y0; in emit_copy_blit()
640 if (dst_tiling == ISL_TILING_Y0) in intelEmitImmediateColorExpandBlit()
743 const bool dst_y_tiled = mt->surf.tiling == ISL_TILING_Y0; in intel_miptree_set_alpha_to_one()
Dintel_pixel_read.c133 irb->mt->surf.tiling != ISL_TILING_Y0)) { in intel_readpixels_tiled_memcpy()
Dintel_tex_image.c236 image->mt->surf.tiling != ISL_TILING_Y0)) { in intel_texsubimage_tiled_memcpy()
789 image->mt->surf.tiling != ISL_TILING_Y0)) { in intel_gettexsubimage_tiled_memcpy()
Dintel_mipmap_tree.c342 tiling == ISL_TILING_Y0) in need_to_retile_as_x()
1174 case ISL_TILING_Y0: in intel_get_tile_dims()
1226 case ISL_TILING_Y0: in intel_miptree_get_aligned_offset()
3100 (devinfo->gen >= 6 && mt->surf.tiling == ISL_TILING_Y0) || in use_intel_mipree_map_blit()
Dbrw_wm_surface_state.c302 case ISL_TILING_Y0: in brw_get_surface_tiling_bits()
/external/mesa3d/src/gallium/drivers/iris/
Diris_resource.c1474 case ISL_TILING_Y0: in iris_resource_get_tile_dims()
1527 case ISL_TILING_Y0: in iris_resource_get_aligned_offset()
/external/mesa3d/src/intel/blorp/
Dblorp_blit.c1667 info->surf.tiling = ISL_TILING_Y0; in blorp_surf_retile_w_to_y()