Home
last modified time | relevance | path

Searched refs:ISL_TILING_Y0_BIT (Results 1 – 9 of 9) sorted by relevance

/external/mesa3d/src/intel/isl/
Disl_gen4.c46 *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT | ISL_TILING_Y0_BIT); in isl_gen4_filter_tiling()
62 ISL_TILING_Y0_BIT : (ISL_TILING_Y0_BIT | ISL_TILING_LINEAR_BIT); in isl_gen4_filter_tiling()
95 *flags &= ~ISL_TILING_Y0_BIT; in isl_gen4_filter_tiling()
Disl_gen7.c232 *flags &= ISL_TILING_Y0_BIT; in isl_gen6_filter_tiling()
236 *flags &= ISL_TILING_Y0_BIT; in isl_gen6_filter_tiling()
256 ISL_TILING_Y0_BIT); in isl_gen6_filter_tiling()
262 ISL_TILING_Y0_BIT | ISL_TILING_Yf_BIT); in isl_gen6_filter_tiling()
298 *flags &= ~ISL_TILING_Y0_BIT; in isl_gen6_filter_tiling()
309 *flags &= ~ISL_TILING_Y0_BIT; in isl_gen6_filter_tiling()
Disl.h490 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0) macro
500 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
Disl.c1959 .tiling_flags = ISL_TILING_Y0_BIT); in isl_surf_get_mcs_surf()
/external/mesa3d/src/intel/isl/tests/
Disl_surf_get_image_offset_test.c145 .tiling_flags = ISL_TILING_Y0_BIT); in test_bdw_2d_r8g8b8a8_unorm_512x512_array01_samples01_noaux_tiley0()
193 .tiling_flags = ISL_TILING_Y0_BIT); in test_bdw_2d_r8g8b8a8_unorm_1024x1024_array06_samples01_noaux_tiley0()
254 .tiling_flags = ISL_TILING_Y0_BIT); in test_bdw_3d_r8g8b8a8_unorm_256x256x256_levels09_tiley0()
/external/mesa3d/src/intel/vulkan/
Danv_android.c486 anv_info.isl_tiling_flags = ISL_TILING_Y0_BIT; in anv_image_from_gralloc()
Danv_image.c1001 isl_tiling_flags = ISL_TILING_Y0_BIT; in resolve_ahw_image()
/external/mesa3d/src/mesa/drivers/dri/i965/
Dintel_mipmap_tree.c488 tiling_flags &= ~ISL_TILING_Y0_BIT; in miptree_create()
598 0, 0, width, height, depth, 1, ISL_TILING_Y0_BIT, in intel_miptree_create_for_bo()
2373 ISL_TILING_Y0_BIT, in intel_update_r8stencil()
/external/mesa3d/src/intel/blorp/
Dblorp_clear.c1380 .tiling_flags = ISL_TILING_Y0_BIT); in blorp_ccs_ambiguate()