1 /* Copyright (c) 2007 Intel Corporation */
2 #include <stdio.h>
3 #include "internal.h"
4
5 /* Register Bit Masks */
6 #define IXGBE_FCTRL_SBP 0x00000002
7 #define IXGBE_FCTRL_MPE 0x00000100
8 #define IXGBE_FCTRL_UPE 0x00000200
9 #define IXGBE_FCTRL_BAM 0x00000400
10 #define IXGBE_FCTRL_PMCF 0x00001000
11 #define IXGBE_FCTRL_DPF 0x00002000
12 #define IXGBE_FCTRL_RPFCE 0x00004000
13 #define IXGBE_FCTRL_RFCE 0x00008000
14 #define IXGBE_VLNCTRL_VET 0x0000FFFF
15 #define IXGBE_VLNCTRL_CFI 0x10000000
16 #define IXGBE_VLNCTRL_CFIEN 0x20000000
17 #define IXGBE_VLNCTRL_VFE 0x40000000
18 #define IXGBE_VLNCTRL_VME 0x80000000
19 #define IXGBE_LINKS_UP 0x40000000
20 #define IXGBE_LINKS_SPEED 0x20000000
21 #define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
22 #define IXGBE_HLREG0_TXCRCEN 0x00000001
23 #define IXGBE_HLREG0_RXCRCSTRP 0x00000002
24 #define IXGBE_HLREG0_JUMBOEN 0x00000004
25 #define IXGBE_HLREG0_TXPADEN 0x00000400
26 #define IXGBE_HLREG0_LPBK 0x00008000
27 #define IXGBE_RMCS_TFCE_802_3X 0x00000008
28 #define IXGBE_RMCS_TFCE_PRIORITY 0x00000010
29 #define IXGBE_FCCFG_TFCE_802_3X 0x00000008
30 #define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010
31 #define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */
32 #define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */
33 #define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */
34 #define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */
35
36 /* Device IDs */
37 #define IXGBE_DEV_ID_82598 0x10B6
38 #define IXGBE_DEV_ID_82598_BX 0x1508
39 #define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
40 #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
41 #define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
42 #define IXGBE_DEV_ID_82598AT 0x10C8
43 #define IXGBE_DEV_ID_82598AT2 0x150B
44 #define IXGBE_DEV_ID_82598EB_CX4 0x10DD
45 #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
46 #define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
47 #define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
48 #define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
49 #define IXGBE_DEV_ID_82599_KX4 0x10F7
50 #define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514
51 #define IXGBE_DEV_ID_82599_KR 0x1517
52 #define IXGBE_DEV_ID_82599_T3_LOM 0x151C
53 #define IXGBE_DEV_ID_82599_CX4 0x10F9
54 #define IXGBE_DEV_ID_82599_SFP 0x10FB
55 #define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152a
56 #define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529
57 #define IXGBE_SUBDEV_ID_82599_SFP 0x11A9
58 #define IXGBE_DEV_ID_82599_SFP_EM 0x1507
59 #define IXGBE_DEV_ID_82599_SFP_SF2 0x154D
60 #define IXGBE_DEV_ID_82599EN_SFP 0x1557
61 #define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
62 #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
63 #define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C
64 #define IXGBE_DEV_ID_82599_LS 0x154F
65 #define IXGBE_DEV_ID_X540T 0x1528
66 #define IXGBE_DEV_ID_82599_SFP_SF_QP 0x154A
67 #define IXGBE_DEV_ID_82599_QSFP_SF_QP 0x1558
68 #define IXGBE_DEV_ID_X540T1 0x1560
69
70 #define IXGBE_DEV_ID_X550T 0x1563
71 #define IXGBE_DEV_ID_X550T1 0x15D1
72 #define IXGBE_DEV_ID_X550EM_X_KX4 0x15AA
73 #define IXGBE_DEV_ID_X550EM_X_KR 0x15AB
74 #define IXGBE_DEV_ID_X550EM_X_SFP 0x15AC
75 #define IXGBE_DEV_ID_X550EM_X_10G_T 0x15AD
76 #define IXGBE_DEV_ID_X550EM_X_1G_T 0x15AE
77 #define IXGBE_DEV_ID_X550EM_A_KR 0x15C2
78 #define IXGBE_DEV_ID_X550EM_A_KR_L 0x15C3
79 #define IXGBE_DEV_ID_X550EM_A_SFP_N 0x15C4
80 #define IXGBE_DEV_ID_X550EM_A_SGMII 0x15C6
81 #define IXGBE_DEV_ID_X550EM_A_SGMII_L 0x15C7
82 #define IXGBE_DEV_ID_X550EM_A_SFP 0x15CE
83
84 /*
85 * Enumerated types specific to the ixgbe hardware
86 * Media Access Controlers
87 */
88 enum ixgbe_mac_type {
89 ixgbe_mac_unknown = 0,
90 ixgbe_mac_82598EB,
91 ixgbe_mac_82599EB,
92 ixgbe_mac_X540,
93 ixgbe_mac_x550,
94 ixgbe_mac_x550em_x,
95 ixgbe_mac_x550em_a,
96 ixgbe_num_macs
97 };
98
99 static enum ixgbe_mac_type
ixgbe_get_mac_type(u16 device_id)100 ixgbe_get_mac_type(u16 device_id)
101 {
102 enum ixgbe_mac_type mac_type = ixgbe_mac_unknown;
103
104 switch (device_id) {
105 case IXGBE_DEV_ID_82598:
106 case IXGBE_DEV_ID_82598_BX:
107 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
108 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
109 case IXGBE_DEV_ID_82598EB_SFP_LOM:
110 case IXGBE_DEV_ID_82598AT:
111 case IXGBE_DEV_ID_82598AT2:
112 case IXGBE_DEV_ID_82598EB_CX4:
113 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
114 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
115 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
116 case IXGBE_DEV_ID_82598EB_XF_LR:
117 mac_type = ixgbe_mac_82598EB;
118 break;
119 case IXGBE_DEV_ID_82599_KX4:
120 case IXGBE_DEV_ID_82599_KX4_MEZZ:
121 case IXGBE_DEV_ID_82599_KR:
122 case IXGBE_DEV_ID_82599_T3_LOM:
123 case IXGBE_DEV_ID_82599_CX4:
124 case IXGBE_DEV_ID_82599_SFP:
125 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
126 case IXGBE_DEV_ID_82599_SFP_FCOE:
127 case IXGBE_SUBDEV_ID_82599_SFP:
128 case IXGBE_DEV_ID_82599_SFP_EM:
129 case IXGBE_DEV_ID_82599_SFP_SF2:
130 case IXGBE_DEV_ID_82599EN_SFP:
131 case IXGBE_DEV_ID_82599_XAUI_LOM:
132 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
133 case IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ:
134 case IXGBE_DEV_ID_82599_LS:
135 case IXGBE_DEV_ID_82599_SFP_SF_QP:
136 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
137 mac_type = ixgbe_mac_82599EB;
138 break;
139 case IXGBE_DEV_ID_X540T:
140 case IXGBE_DEV_ID_X540T1:
141 mac_type = ixgbe_mac_X540;
142 break;
143 case IXGBE_DEV_ID_X550T:
144 case IXGBE_DEV_ID_X550T1:
145 mac_type = ixgbe_mac_x550;
146 break;
147 case IXGBE_DEV_ID_X550EM_X_KX4:
148 case IXGBE_DEV_ID_X550EM_X_KR:
149 case IXGBE_DEV_ID_X550EM_X_SFP:
150 case IXGBE_DEV_ID_X550EM_X_10G_T:
151 case IXGBE_DEV_ID_X550EM_X_1G_T:
152 mac_type = ixgbe_mac_x550em_x;
153 break;
154 case IXGBE_DEV_ID_X550EM_A_KR:
155 case IXGBE_DEV_ID_X550EM_A_KR_L:
156 case IXGBE_DEV_ID_X550EM_A_SFP_N:
157 case IXGBE_DEV_ID_X550EM_A_SGMII:
158 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
159 case IXGBE_DEV_ID_X550EM_A_SFP:
160 mac_type = ixgbe_mac_x550em_a;
161 break;
162 default:
163 mac_type = ixgbe_mac_82598EB;
164 break;
165 }
166
167 return mac_type;
168 }
169
170 int
ixgbe_dump_regs(struct ethtool_drvinfo * info maybe_unused,struct ethtool_regs * regs)171 ixgbe_dump_regs(struct ethtool_drvinfo *info maybe_unused,
172 struct ethtool_regs *regs)
173 {
174 u32 *regs_buff = (u32 *)regs->data;
175 u32 regs_buff_len = regs->len / sizeof(*regs_buff);
176 u32 reg;
177 u32 offset;
178 u16 hw_device_id = (u16) regs->version;
179 u8 version = (u8)(regs->version >> 24);
180 u8 i;
181 enum ixgbe_mac_type mac_type;
182
183 if (version == 0)
184 return -1;
185
186 /* The current driver reports the MAC type, but older versions
187 * only report the device ID so we have to infer the MAC type.
188 */
189 mac_type = version > 1 ? version : ixgbe_get_mac_type(hw_device_id);
190
191 reg = regs_buff[1065];
192 fprintf(stdout,
193 "0x042A4: LINKS (Link Status register) 0x%08X\n"
194 " Link Status: %s\n"
195 " Link Speed: %s\n",
196 reg,
197 reg & IXGBE_LINKS_UP ? "up" : "down",
198 reg & IXGBE_LINKS_SPEED ? "10G" : "1G");
199
200 reg = regs_buff[515];
201 fprintf(stdout,
202 "0x05080: FCTRL (Filter Control register) 0x%08X\n"
203 " Broadcast Accept: %s\n"
204 " Unicast Promiscuous: %s\n"
205 " Multicast Promiscuous: %s\n"
206 " Store Bad Packets: %s\n",
207 reg,
208 reg & IXGBE_FCTRL_BAM ? "enabled" : "disabled",
209 reg & IXGBE_FCTRL_UPE ? "enabled" : "disabled",
210 reg & IXGBE_FCTRL_MPE ? "enabled" : "disabled",
211 reg & IXGBE_FCTRL_SBP ? "enabled" : "disabled");
212
213 /* Some FCTRL bits are valid only on 82598 */
214 if (mac_type == ixgbe_mac_82598EB) {
215 fprintf(stdout,
216 " Receive Flow Control Packets: %s\n"
217 " Receive Priority Flow Control Packets: %s\n"
218 " Discard Pause Frames: %s\n"
219 " Pass MAC Control Frames: %s\n",
220 reg & IXGBE_FCTRL_RFCE ? "enabled" : "disabled",
221 reg & IXGBE_FCTRL_RPFCE ? "enabled" : "disabled",
222 reg & IXGBE_FCTRL_DPF ? "enabled" : "disabled",
223 reg & IXGBE_FCTRL_PMCF ? "enabled" : "disabled");
224 }
225
226 reg = regs_buff[1128];
227 if (mac_type >= ixgbe_mac_82599EB) {
228 fprintf(stdout,
229 "0x04294: MFLCN (TabMAC Flow Control register) 0x%08X\n"
230 " Receive Flow Control Packets: %s\n"
231 " Discard Pause Frames: %s\n"
232 " Pass MAC Control Frames: %s\n"
233 " Receive Priority Flow Control Packets: %s\n",
234 reg,
235 reg & IXGBE_MFLCN_RFCE ? "enabled" : "disabled",
236 reg & IXGBE_MFLCN_DPF ? "enabled" : "disabled",
237 reg & IXGBE_MFLCN_PMCF ? "enabled" : "disabled",
238 reg & IXGBE_MFLCN_RPFCE ? "enabled" : "disabled");
239 }
240
241 reg = regs_buff[516];
242 fprintf(stdout,
243 "0x05088: VLNCTRL (VLAN Control register) 0x%08X\n"
244 " VLAN Mode: %s\n"
245 " VLAN Filter: %s\n",
246 reg,
247 reg & IXGBE_VLNCTRL_VME ? "enabled" : "disabled",
248 reg & IXGBE_VLNCTRL_VFE ? "enabled" : "disabled");
249
250 reg = regs_buff[437];
251 fprintf(stdout,
252 "0x02100: SRRCTL0 (Split and Replic Rx Control 0) 0x%08X\n"
253 " Receive Buffer Size: %uKB\n",
254 reg,
255 (reg & IXGBE_SRRCTL_BSIZEPKT_MASK) <= 0x10 ? (reg & IXGBE_SRRCTL_BSIZEPKT_MASK) : 0x10);
256
257 reg = regs_buff[829];
258 if (mac_type == ixgbe_mac_82598EB) {
259 fprintf(stdout,
260 "0x03D00: RMCS (Receive Music Control register) 0x%08X\n"
261 " Transmit Flow Control: %s\n"
262 " Priority Flow Control: %s\n",
263 reg,
264 reg & IXGBE_RMCS_TFCE_802_3X ? "enabled" : "disabled",
265 reg & IXGBE_RMCS_TFCE_PRIORITY ? "enabled" : "disabled");
266 } else if (mac_type >= ixgbe_mac_82599EB) {
267 fprintf(stdout,
268 "0x03D00: FCCFG (Flow Control Configuration) 0x%08X\n"
269 " Transmit Flow Control: %s\n"
270 " Priority Flow Control: %s\n",
271 reg,
272 reg & IXGBE_FCCFG_TFCE_802_3X ? "enabled" : "disabled",
273 reg & IXGBE_FCCFG_TFCE_PRIORITY ? "enabled" : "disabled");
274 }
275
276 reg = regs_buff[1047];
277 fprintf(stdout,
278 "0x04240: HLREG0 (Highlander Control 0 register) 0x%08X\n"
279 " Transmit CRC: %s\n"
280 " Receive CRC Strip: %s\n"
281 " Jumbo Frames: %s\n"
282 " Pad Short Frames: %s\n"
283 " Loopback: %s\n",
284 reg,
285 reg & IXGBE_HLREG0_TXCRCEN ? "enabled" : "disabled",
286 reg & IXGBE_HLREG0_RXCRCSTRP ? "enabled" : "disabled",
287 reg & IXGBE_HLREG0_JUMBOEN ? "enabled" : "disabled",
288 reg & IXGBE_HLREG0_TXPADEN ? "enabled" : "disabled",
289 reg & IXGBE_HLREG0_LPBK ? "enabled" : "disabled");
290
291 /* General Registers */
292 fprintf(stdout,
293 "0x00000: CTRL (Device Control) 0x%08X\n",
294 regs_buff[0]);
295
296 fprintf(stdout,
297 "0x00008: STATUS (Device Status) 0x%08X\n",
298 regs_buff[1]);
299
300 fprintf(stdout,
301 "0x00018: CTRL_EXT (Extended Device Control) 0x%08X\n",
302 regs_buff[2]);
303
304 fprintf(stdout,
305 "0x00020: ESDP (Extended SDP Control) 0x%08X\n",
306 regs_buff[3]);
307
308 fprintf(stdout,
309 "0x00028: EODSDP (Extended OD SDP Control) 0x%08X\n",
310 regs_buff[4]);
311
312 fprintf(stdout,
313 "0x00200: LEDCTL (LED Control) 0x%08X\n",
314 regs_buff[5]);
315
316 fprintf(stdout,
317 "0x00048: FRTIMER (Free Running Timer) 0x%08X\n",
318 regs_buff[6]);
319
320 fprintf(stdout,
321 "0x0004C: TCPTIMER (TCP Timer) 0x%08X\n",
322 regs_buff[7]);
323
324 /* NVM Register */
325 offset = mac_type == ixgbe_mac_x550em_a ? 0x15FF8 : 0x10010;
326 fprintf(stdout,
327 "0x%05X: EEC (EEPROM/Flash Control) 0x%08X\n",
328 offset, regs_buff[8]);
329
330 fprintf(stdout,
331 "0x10014: EERD (EEPROM Read) 0x%08X\n",
332 regs_buff[9]);
333
334 offset = mac_type == ixgbe_mac_x550em_a ? 0x15F6C : 0x1001C;
335 fprintf(stdout,
336 "0x%05X: FLA (Flash Access) 0x%08X\n",
337 offset, regs_buff[10]);
338
339 fprintf(stdout,
340 "0x10110: EEMNGCTL (Manageability EEPROM Control) 0x%08X\n",
341 regs_buff[11]);
342
343 fprintf(stdout,
344 "0x10114: EEMNGDATA (Manageability EEPROM R/W Data) 0x%08X\n",
345 regs_buff[12]);
346
347 fprintf(stdout,
348 "0x10118: FLMNGCTL (Manageability Flash Control) 0x%08X\n",
349 regs_buff[13]);
350
351 fprintf(stdout,
352 "0x1011C: FLMNGDATA (Manageability Flash Read Data) 0x%08X\n",
353 regs_buff[14]);
354
355 fprintf(stdout,
356 "0x10120: FLMNGCNT (Manageability Flash Read Count) 0x%08X\n",
357 regs_buff[15]);
358
359 fprintf(stdout,
360 "0x1013C: FLOP (Flash Opcode) 0x%08X\n",
361 regs_buff[16]);
362
363 offset = mac_type == ixgbe_mac_x550em_a ? 0x15F64 : 0x10200;
364 fprintf(stdout,
365 "0x%05X: GRC (General Receive Control) 0x%08X\n",
366 offset, regs_buff[17]);
367
368 /* Interrupt */
369 fprintf(stdout,
370 "0x00800: EICR (Extended Interrupt Cause) 0x%08X\n",
371 regs_buff[18]);
372
373 fprintf(stdout,
374 "0x00808: EICS (Extended Interrupt Cause Set) 0x%08X\n",
375 regs_buff[19]);
376
377 fprintf(stdout,
378 "0x00880: EIMS (Extended Interr. Mask Set/Read) 0x%08X\n",
379 regs_buff[20]);
380
381 fprintf(stdout,
382 "0x00888: EIMC (Extended Interrupt Mask Clear) 0x%08X\n",
383 regs_buff[21]);
384
385 fprintf(stdout,
386 "0x00810: EIAC (Extended Interrupt Auto Clear) 0x%08X\n",
387 regs_buff[22]);
388
389 fprintf(stdout,
390 "0x00890: EIAM (Extended Interr. Auto Mask EN) 0x%08X\n",
391 regs_buff[23]);
392
393 fprintf(stdout,
394 "0x00820: EITR0 (Extended Interrupt Throttle 0) 0x%08X\n",
395 regs_buff[24]);
396
397 fprintf(stdout,
398 "0x00900: IVAR0 (Interrupt Vector Allocation 0) 0x%08X\n",
399 regs_buff[25]);
400
401 fprintf(stdout,
402 "0x00000: MSIXT (MSI-X Table) 0x%08X\n",
403 regs_buff[26]);
404
405 if (mac_type == ixgbe_mac_82598EB)
406 fprintf(stdout,
407 "0x02000: MSIXPBA (MSI-X Pending Bit Array) 0x%08X\n",
408 regs_buff[27]);
409
410 fprintf(stdout,
411 "0x11068: PBACL (MSI-X PBA Clear) 0x%08X\n",
412 regs_buff[28]);
413
414 fprintf(stdout,
415 "0x00898: GPIE (General Purpose Interrupt EN) 0x%08X\n",
416 regs_buff[29]);
417
418 /* Flow Control */
419 fprintf(stdout,
420 "0x03008: PFCTOP (Priority Flow Ctrl Type Opcode) 0x%08X\n",
421 regs_buff[30]);
422
423 for (i = 0; i < 4; i++)
424 fprintf(stdout,
425 "0x%05X: FCCTV%d (Flow Ctrl Tx Timer Value %d) 0x%08X\n",
426 0x03200 + (4 * i), i, i, regs_buff[31 + i]);
427
428 for (i = 0; i < 8; i++)
429 fprintf(stdout,
430 "0x%05X: FCRTL%d (Flow Ctrl Rx Threshold low %d) 0x%08X\n",
431 0x3220 + (8 * i), i, i, regs_buff[35 + i]);
432
433 for (i = 0; i < 8; i++)
434 fprintf(stdout,
435 "0x%05X: FCRTH%d (Flow Ctrl Rx Threshold High %d) 0x%08X\n",
436 0x3260 + (8 * i), i, i, regs_buff[43 + i]);
437
438 fprintf(stdout,
439 "0x032A0: FCRTV (Flow Control Refresh Threshold) 0x%08X\n",
440 regs_buff[51]);
441
442 fprintf(stdout,
443 "0x0CE00: TFCS (Transmit Flow Control Status) 0x%08X\n",
444 regs_buff[52]);
445
446 /* Receive DMA */
447 for (i = 0; i < 64; i++)
448 fprintf(stdout,
449 "0x%05X: RDBAL%02d (Rx Desc Base Addr Low %02d) 0x%08X\n",
450 0x01000 + (0x40 * i), i, i, regs_buff[53 + i]);
451
452 for (i = 0; i < 64; i++)
453 fprintf(stdout,
454 "0x%05X: RDBAH%02d (Rx Desc Base Addr High %02d) 0x%08X\n",
455 0x01004 + (0x40 * i), i, i, regs_buff[117 + i]);
456
457 for (i = 0; i < 64; i++)
458 fprintf(stdout,
459 "0x%05X: RDLEN%02d (Receive Descriptor Length %02d) 0x%08X\n",
460 0x01008 + (0x40 * i), i, i, regs_buff[181 + i]);
461
462 for (i = 0; i < 64; i++)
463 fprintf(stdout,
464 "0x%05X: RDH%02d (Receive Descriptor Head %02d) 0x%08X\n",
465 0x01010 + (0x40 * i), i, i, regs_buff[245 + i]);
466
467 for (i = 0; i < 64; i++)
468 fprintf(stdout,
469 "0x%05X: RDT%02d (Receive Descriptor Tail %02d) 0x%08X\n",
470 0x01018 + (0x40 * i), i, i, regs_buff[309 + i]);
471
472 for (i = 0; i < 64; i++)
473 fprintf(stdout,
474 "0x%05X: RXDCTL%02d (Receive Descriptor Control %02d) 0x%08X\n",
475 0x01028 + (0x40 * i), i, i, regs_buff[373 + i]);
476
477 for (i = 0; i < 16; i++)
478 fprintf(stdout,
479 "0x%05X: SRRCTL%02d (Split and Replic Rx Control %02d) 0x%08X\n",
480 0x02100 + (4 * i), i, i, regs_buff[437 + i]);
481
482 for (i = 0; i < 16; i++)
483 fprintf(stdout,
484 "0x%05X: DCA_RXCTRL%02d (Rx DCA Control %02d) 0x%08X\n",
485 0x02200 + (4 * i), i, i, regs_buff[453 + i]);
486
487 fprintf(stdout,
488 "0x02F00: RDRXCTL (Receive DMA Control) 0x%08X\n",
489 regs_buff[469]);
490
491 for (i = 0; i < 8; i++)
492 fprintf(stdout,
493 "0x%05X: RXPBSIZE%d (Receive Packet Buffer Size %d) 0x%08X\n",
494 0x3C00 + (4 * i), i, i, regs_buff[470 + i]);
495
496 fprintf(stdout,
497 "0x03000: RXCTRL (Receive Control) 0x%08X\n",
498 regs_buff[478]);
499
500 if (mac_type == ixgbe_mac_82598EB)
501 fprintf(stdout,
502 "0x03D04: DROPEN (Drop Enable Control) 0x%08X\n",
503 regs_buff[479]);
504
505 /* Receive */
506 fprintf(stdout,
507 "0x05000: RXCSUM (Receive Checksum Control) 0x%08X\n",
508 regs_buff[480]);
509
510 fprintf(stdout,
511 "0x05008: RFCTL (Receive Filter Control) 0x%08X\n",
512 regs_buff[481]);
513
514 for (i = 0; i < 16; i++)
515 fprintf(stdout,
516 "0x%05X: RAL%02d (Receive Address Low%02d) 0x%08X\n",
517 0x05400 + (8 * i), i, i, regs_buff[482 + i]);
518
519 for (i = 0; i < 16; i++)
520 fprintf(stdout,
521 "0x%05X: RAH%02d (Receive Address High %02d) 0x%08X\n",
522 0x05404 + (8 * i), i, i, regs_buff[498 + i]);
523
524 fprintf(stdout,
525 "0x05480: PSRTYPE (Packet Split Receive Type) 0x%08X\n",
526 regs_buff[514]);
527
528 fprintf(stdout,
529 "0x05090: MCSTCTRL (Multicast Control) 0x%08X\n",
530 regs_buff[517]);
531
532 fprintf(stdout,
533 "0x05818: MRQC (Multiple Rx Queues Command) 0x%08X\n",
534 regs_buff[518]);
535
536 fprintf(stdout,
537 "0x0581C: VMD_CTL (VMDq Control) 0x%08X\n",
538 regs_buff[519]);
539
540 for (i = 0; i < 8; i++)
541 fprintf(stdout,
542 "0x%05X: IMIR%d (Immediate Interrupt Rx %d) 0x%08X\n",
543 0x05A80 + (4 * i), i, i, regs_buff[520 + i]);
544
545 for (i = 0; i < 8; i++)
546 fprintf(stdout,
547 "0x%05X: IMIREXT%d (Immed. Interr. Rx Extended %d) 0x%08X\n",
548 0x05AA0 + (4 * i), i, i, regs_buff[528 + i]);
549
550 fprintf(stdout,
551 "0x05AC0: IMIRVP (Immed. Interr. Rx VLAN Prior.) 0x%08X\n",
552 regs_buff[536]);
553
554 /* Transmit */
555 for (i = 0; i < 32; i++)
556 fprintf(stdout,
557 "0x%05X: TDBAL%02d (Tx Desc Base Addr Low %02d) 0x%08X\n",
558 0x06000 + (0x40 * i), i, i, regs_buff[537 + i]);
559
560 for (i = 0; i < 32; i++)
561 fprintf(stdout,
562 "0x%05X: TDBAH%02d (Tx Desc Base Addr High %02d) 0x%08X\n",
563 0x06004 + (0x40 * i), i, i, regs_buff[569 + i]);
564
565 for (i = 0; i < 32; i++)
566 fprintf(stdout,
567 "0x%05X: TDLEN%02d (Tx Descriptor Length %02d) 0x%08X\n",
568 0x06008 + (0x40 * i), i, i, regs_buff[601 + i]);
569
570 for (i = 0; i < 32; i++)
571 fprintf(stdout,
572 "0x%05X: TDH%02d (Transmit Descriptor Head %02d) 0x%08X\n",
573 0x06010 + (0x40 * i), i, i, regs_buff[633 + i]);
574
575 for (i = 0; i < 32; i++)
576 fprintf(stdout,
577 "0x%05X: TDT%02d (Transmit Descriptor Tail %02d) 0x%08X\n",
578 0x06018 + (0x40 * i), i, i, regs_buff[665 + i]);
579
580 for (i = 0; i < 32; i++)
581 fprintf(stdout,
582 "0x%05X: TXDCTL%02d (Tx Descriptor Control %02d) 0x%08X\n",
583 0x06028 + (0x40 * i), i, i, regs_buff[697 + i]);
584
585 for (i = 0; i < 32; i++)
586 fprintf(stdout,
587 "0x%05X: TDWBAL%02d (Tx Desc Compl. WB Addr low %02d) 0x%08X\n",
588 0x06038 + (0x40 * i), i, i, regs_buff[729 + i]);
589
590 for (i = 0; i < 32; i++)
591 fprintf(stdout,
592 "0x%05X: TDWBAH%02d (Tx Desc Compl. WB Addr High %02d) 0x%08X\n",
593 0x0603C + (0x40 * i), i, i, regs_buff[761 + i]);
594
595 fprintf(stdout,
596 "0x07E00: DTXCTL (DMA Tx Control) 0x%08X\n",
597 regs_buff[793]);
598
599 for (i = 0; i < 16; i++)
600 fprintf(stdout,
601 "0x%05X: DCA_TXCTRL%02d (Tx DCA Control %02d) 0x%08X\n",
602 0x07200 + (4 * i), i, i, regs_buff[794 + i]);
603
604 if (mac_type == ixgbe_mac_82598EB)
605 fprintf(stdout,
606 "0x0CB00: TIPG (Transmit IPG Control) 0x%08X\n",
607 regs_buff[810]);
608
609 for (i = 0; i < 8; i++)
610 fprintf(stdout,
611 "0x%05X: TXPBSIZE%d (Transmit Packet Buffer Size %d) 0x%08X\n",
612 0x0CC00 + (4 * i), i, i, regs_buff[811 + i]);
613
614 fprintf(stdout,
615 "0x0CD10: MNGTXMAP (Manageability Tx TC Mapping) 0x%08X\n",
616 regs_buff[819]);
617
618 /* Wake Up */
619 fprintf(stdout,
620 "0x05800: WUC (Wake up Control) 0x%08X\n",
621 regs_buff[820]);
622
623 fprintf(stdout,
624 "0x05808: WUFC (Wake Up Filter Control) 0x%08X\n",
625 regs_buff[821]);
626
627 fprintf(stdout,
628 "0x05810: WUS (Wake Up Status) 0x%08X\n",
629 regs_buff[822]);
630
631 fprintf(stdout,
632 "0x05838: IPAV (IP Address Valid) 0x%08X\n",
633 regs_buff[823]);
634
635 fprintf(stdout,
636 "0x05840: IP4AT (IPv4 Address Table) 0x%08X\n",
637 regs_buff[824]);
638
639 fprintf(stdout,
640 "0x05880: IP6AT (IPv6 Address Table) 0x%08X\n",
641 regs_buff[825]);
642
643 fprintf(stdout,
644 "0x05900: WUPL (Wake Up Packet Length) 0x%08X\n",
645 regs_buff[826]);
646
647 fprintf(stdout,
648 "0x05A00: WUPM (Wake Up Packet Memory) 0x%08X\n",
649 regs_buff[827]);
650
651 fprintf(stdout,
652 "0x09000: FHFT (Flexible Host Filter Table) 0x%08X\n",
653 regs_buff[828]);
654
655 /* DCB */
656 if (mac_type == ixgbe_mac_82598EB) {
657 fprintf(stdout,
658 "0x07F40: DPMCS (Desc. Plan Music Ctrl Status) 0x%08X\n",
659 regs_buff[830]);
660
661 fprintf(stdout,
662 "0x0CD00: PDPMCS (Pkt Data Plan Music ctrl Stat) 0x%08X\n",
663 regs_buff[831]);
664
665 fprintf(stdout,
666 "0x050A0: RUPPBMR (Rx User Prior to Pkt Buff Map) 0x%08X\n",
667 regs_buff[832]);
668
669 for (i = 0; i < 8; i++)
670 fprintf(stdout,
671 "0x%05X: RT2CR%d (Receive T2 Configure %d) 0x%08X\n",
672 0x03C20 + (4 * i), i, i, regs_buff[833 + i]);
673
674 for (i = 0; i < 8; i++)
675 fprintf(stdout,
676 "0x%05X: RT2SR%d (Receive T2 Status %d) 0x%08X\n",
677 0x03C40 + (4 * i), i, i, regs_buff[841 + i]);
678
679 for (i = 0; i < 8; i++)
680 fprintf(stdout,
681 "0x%05X: TDTQ2TCCR%d (Tx Desc TQ2 TC Config %d) 0x%08X\n",
682 0x0602C + (0x40 * i), i, i, regs_buff[849 + i]);
683
684 for (i = 0; i < 8; i++)
685 fprintf(stdout,
686 "0x%05X: TDTQ2TCSR%d (Tx Desc TQ2 TC Status %d) 0x%08X\n",
687 0x0622C + (0x40 * i), i, i, regs_buff[857 + i]);
688
689 for (i = 0; i < 8; i++)
690 fprintf(stdout,
691 "0x%05X: TDPT2TCCR%d (Tx Data Plane T2 TC Config %d) 0x%08X\n",
692 0x0CD20 + (4 * i), i, i, regs_buff[865 + i]);
693
694 for (i = 0; i < 8; i++)
695 fprintf(stdout,
696 "0x%05X: TDPT2TCSR%d (Tx Data Plane T2 TC Status %d) 0x%08X\n",
697 0x0CD40 + (4 * i), i, i, regs_buff[873 + i]);
698 } else if (mac_type >= ixgbe_mac_82599EB && mac_type <= ixgbe_mac_x550) {
699 fprintf(stdout,
700 "0x04900: RTTDCS (Tx Descr Plane Ctrl&Status) 0x%08X\n",
701 regs_buff[830]);
702
703 fprintf(stdout,
704 "0x0CD00: RTTPCS (Tx Pkt Plane Ctrl&Status) 0x%08X\n",
705 regs_buff[831]);
706
707 fprintf(stdout,
708 "0x02430: RTRPCS (Rx Packet Plane Ctrl&Status) 0x%08X\n",
709 regs_buff[832]);
710
711 for (i = 0; i < 8; i++)
712 fprintf(stdout,
713 "0x%05X: RTRPT4C%d (Rx Packet Plane T4 Config %d) 0x%08X\n",
714 0x02140 + (4 * i), i, i, regs_buff[833 + i]);
715
716 for (i = 0; i < 8; i++)
717 fprintf(stdout,
718 "0x%05X: RTRPT4S%d (Rx Packet Plane T4 Status %d) 0x%08X\n",
719 0x02160 + (4 * i), i, i, regs_buff[841 + i]);
720
721 for (i = 0; i < 8; i++)
722 fprintf(stdout,
723 "0x%05X: RTTDT2C%d (Tx Descr Plane T2 Config %d) 0x%08X\n",
724 0x04910 + (4 * i), i, i, regs_buff[849 + i]);
725
726 if (mac_type < ixgbe_mac_x550)
727 for (i = 0; i < 8; i++)
728 fprintf(stdout,
729 "0x%05X: RTTDT2S%d (Tx Descr Plane T2 Status %d) 0x%08X\n",
730 0x04930 + (4 * i), i, i, regs_buff[857 + i]);
731
732 for (i = 0; i < 8; i++)
733 fprintf(stdout,
734 "0x%05X: RTTPT2C%d (Tx Packet Plane T2 Config %d) 0x%08X\n",
735 0x0CD20 + (4 * i), i, i, regs_buff[865]);
736
737 if (mac_type < ixgbe_mac_x550)
738 for (i = 0; i < 8; i++)
739 fprintf(stdout,
740 "0x%05X: RTTPT2S%d (Tx Packet Plane T2 Status %d) 0x%08X\n",
741 0x0CD40 + (4 * i), i, i, regs_buff[873 + i]);
742 }
743
744 if (regs_buff_len > 1129 && mac_type != ixgbe_mac_82598EB) {
745 fprintf(stdout,
746 "0x03020: RTRUP2TC (Rx User Prio to Traffic Classes)0x%08X\n",
747 regs_buff[1129]);
748
749 fprintf(stdout,
750 "0x0C800: RTTUP2TC (Tx User Prio to Traffic Classes)0x%08X\n",
751 regs_buff[1130]);
752
753 if (mac_type <= ixgbe_mac_x550)
754 for (i = 0; i < 4; i++)
755 fprintf(stdout,
756 "0x%05X: TXLLQ%d (Strict Low Lat Tx Queues %d) 0x%08X\n",
757 0x082E0 + (4 * i), i, i, regs_buff[1131 + i]);
758
759 if (mac_type == ixgbe_mac_82599EB) {
760 fprintf(stdout,
761 "0x04980: RTTBCNRM (DCB TX Rate Sched MMW) 0x%08X\n",
762 regs_buff[1135]);
763
764 fprintf(stdout,
765 "0x0498C: RTTBCNRD (DCB TX Rate-Scheduler Drift) 0x%08X\n",
766 regs_buff[1136]);
767 } else if (mac_type <= ixgbe_mac_x550) {
768 fprintf(stdout,
769 "0x04980: RTTQCNRM (DCB TX QCN Rate Sched MMW) 0x%08X\n",
770 regs_buff[1135]);
771
772 fprintf(stdout,
773 "0x0498C: RTTQCNRR (DCB TX QCN Rate Reset) 0x%08X\n",
774 regs_buff[1136]);
775
776 if (mac_type < ixgbe_mac_x550)
777 fprintf(stdout,
778 "0x08B00: RTTQCNCR (DCB TX QCN Control) 0x%08X\n",
779 regs_buff[1137]);
780
781 fprintf(stdout,
782 "0x04A90: RTTQCNTG (DCB TX QCN Tagging) 0x%08X\n",
783 regs_buff[1138]);
784 }
785 }
786
787 /* Statistics */
788 fprintf(stdout,
789 "0x04000: crcerrs (CRC Error Count) 0x%08X\n",
790 regs_buff[881]);
791
792 fprintf(stdout,
793 "0x04004: illerrc (Illegal Byte Error Count) 0x%08X\n",
794 regs_buff[882]);
795
796 fprintf(stdout,
797 "0x04008: errbc (Error Byte Count) 0x%08X\n",
798 regs_buff[883]);
799
800 fprintf(stdout,
801 "0x04010: mspdc (MAC Short Packet Discard Count) 0x%08X\n",
802 regs_buff[884]);
803
804 for (i = 0; i < 8; i++)
805 fprintf(stdout,
806 "0x%05X: mpc%d (Missed Packets Count %d) 0x%08X\n",
807 0x03FA0 + (4 * i), i, i, regs_buff[885 + i]);
808
809 fprintf(stdout,
810 "0x04034: mlfc (MAC Local Fault Count) 0x%08X\n",
811 regs_buff[893]);
812
813 fprintf(stdout,
814 "0x04038: mrfc (MAC Remote Fault Count) 0x%08X\n",
815 regs_buff[894]);
816
817 fprintf(stdout,
818 "0x04040: rlec (Receive Length Error Count) 0x%08X\n",
819 regs_buff[895]);
820
821 fprintf(stdout,
822 "0x03F60: lxontxc (Link XON Transmitted Count) 0x%08X\n",
823 regs_buff[896]);
824
825 fprintf(stdout,
826 "0x0CF60: lxonrxc (Link XON Received Count) 0x%08X\n",
827 regs_buff[897]);
828
829 fprintf(stdout,
830 "0x03F68: lxofftxc (Link XOFF Transmitted Count) 0x%08X\n",
831 regs_buff[898]);
832
833 fprintf(stdout,
834 "0x0CF68: lxoffrxc (Link XOFF Received Count) 0x%08X\n",
835 regs_buff[899]);
836
837 for (i = 0; i < 8; i++)
838 fprintf(stdout,
839 "0x%05X: pxontxc%d (Priority XON Tx Count %d) 0x%08X\n",
840 0x03F00 + (4 * i), i, i, regs_buff[900 + i]);
841
842 for (i = 0; i < 8; i++)
843 fprintf(stdout,
844 "0x%05X: pxonrxc%d (Priority XON Received Count %d) 0x%08X\n",
845 0x0CF00 + (4 * i), i, i, regs_buff[908 + i]);
846
847 for (i = 0; i < 8; i++)
848 fprintf(stdout,
849 "0x%05X: pxofftxc%d (Priority XOFF Tx Count %d) 0x%08X\n",
850 0x03F20 + (4 * i), i, i, regs_buff[916 + i]);
851
852 for (i = 0; i < 8; i++)
853 fprintf(stdout,
854 "0x%05X: pxoffrxc%d (Priority XOFF Received Count %d) 0x%08X\n",
855 0x0CF20 + (4 * i), i, i, regs_buff[924 + i]);
856
857 fprintf(stdout,
858 "0x0405C: prc64 (Packets Received (64B) Count) 0x%08X\n",
859 regs_buff[932]);
860
861 fprintf(stdout,
862 "0x04060: prc127 (Packets Rx (65-127B) Count) 0x%08X\n",
863 regs_buff[933]);
864
865 fprintf(stdout,
866 "0x04064: prc255 (Packets Rx (128-255B) Count) 0x%08X\n",
867 regs_buff[934]);
868
869 fprintf(stdout,
870 "0x04068: prc511 (Packets Rx (256-511B) Count) 0x%08X\n",
871 regs_buff[935]);
872
873 fprintf(stdout,
874 "0x0406C: prc1023 (Packets Rx (512-1023B) Count) 0x%08X\n",
875 regs_buff[936]);
876
877 fprintf(stdout,
878 "0x04070: prc1522 (Packets Rx (1024-Max) Count) 0x%08X\n",
879 regs_buff[937]);
880
881 fprintf(stdout,
882 "0x04074: gprc (Good Packets Received Count) 0x%08X\n",
883 regs_buff[938]);
884
885 fprintf(stdout,
886 "0x04078: bprc (Broadcast Packets Rx Count) 0x%08X\n",
887 regs_buff[939]);
888
889 fprintf(stdout,
890 "0x0407C: mprc (Multicast Packets Rx Count) 0x%08X\n",
891 regs_buff[940]);
892
893 fprintf(stdout,
894 "0x04080: gptc (Good Packets Transmitted Count) 0x%08X\n",
895 regs_buff[941]);
896
897 fprintf(stdout,
898 "0x04088: gorcl (Good Octets Rx Count Low) 0x%08X\n",
899 regs_buff[942]);
900
901 fprintf(stdout,
902 "0x0408C: gorch (Good Octets Rx Count High) 0x%08X\n",
903 regs_buff[943]);
904
905 fprintf(stdout,
906 "0x04090: gotcl (Good Octets Tx Count Low) 0x%08X\n",
907 regs_buff[944]);
908
909 fprintf(stdout,
910 "0x04094: gotch (Good Octets Tx Count High) 0x%08X\n",
911 regs_buff[945]);
912
913 for (i = 0; i < 8; i++)
914 fprintf(stdout,
915 "0x%05X: rnbc%d (Receive No Buffers Count %d) 0x%08X\n",
916 0x03FC0 + (4 * i), i, i, regs_buff[946 + i]);
917
918 fprintf(stdout,
919 "0x040A4: ruc (Receive Undersize count) 0x%08X\n",
920 regs_buff[954]);
921
922 fprintf(stdout,
923 "0x040A8: rfc (Receive Fragment Count) 0x%08X\n",
924 regs_buff[955]);
925
926 fprintf(stdout,
927 "0x040AC: roc (Receive Oversize Count) 0x%08X\n",
928 regs_buff[956]);
929
930 fprintf(stdout,
931 "0x040B0: rjc (Receive Jabber Count) 0x%08X\n",
932 regs_buff[957]);
933
934 fprintf(stdout,
935 "0x040B4: mngprc (Management Packets Rx Count) 0x%08X\n",
936 regs_buff[958]);
937
938 fprintf(stdout,
939 "0x040B8: mngpdc (Management Pkts Dropped Count) 0x%08X\n",
940 regs_buff[959]);
941
942 fprintf(stdout,
943 "0x0CF90: mngptc (Management Packets Tx Count) 0x%08X\n",
944 regs_buff[960]);
945
946 fprintf(stdout,
947 "0x040C0: torl (Total Octets Rx Count Low) 0x%08X\n",
948 regs_buff[961]);
949
950 fprintf(stdout,
951 "0x040C4: torh (Total Octets Rx Count High) 0x%08X\n",
952 regs_buff[962]);
953
954 fprintf(stdout,
955 "0x040D0: tpr (Total Packets Received) 0x%08X\n",
956 regs_buff[963]);
957
958 fprintf(stdout,
959 "0x040D4: tpt (Total Packets Transmitted) 0x%08X\n",
960 regs_buff[964]);
961
962 fprintf(stdout,
963 "0x040D8: ptc64 (Packets Tx (64B) Count) 0x%08X\n",
964 regs_buff[965]);
965
966 fprintf(stdout,
967 "0x040DC: ptc127 (Packets Tx (65-127B) Count) 0x%08X\n",
968 regs_buff[966]);
969
970 fprintf(stdout,
971 "0x040E0: ptc255 (Packets Tx (128-255B) Count) 0x%08X\n",
972 regs_buff[967]);
973
974 fprintf(stdout,
975 "0x040E4: ptc511 (Packets Tx (256-511B) Count) 0x%08X\n",
976 regs_buff[968]);
977
978 fprintf(stdout,
979 "0x040E8: ptc1023 (Packets Tx (512-1023B) Count) 0x%08X\n",
980 regs_buff[969]);
981
982 fprintf(stdout,
983 "0x040EC: ptc1522 (Packets Tx (1024-Max) Count) 0x%08X\n",
984 regs_buff[970]);
985
986 fprintf(stdout,
987 "0x040F0: mptc (Multicast Packets Tx Count) 0x%08X\n",
988 regs_buff[971]);
989
990 fprintf(stdout,
991 "0x040F4: bptc (Broadcast Packets Tx Count) 0x%08X\n",
992 regs_buff[972]);
993
994 fprintf(stdout,
995 "0x04120: xec (XSUM Error Count) 0x%08X\n",
996 regs_buff[973]);
997
998 for (i = 0; i < 16; i++)
999 fprintf(stdout,
1000 "0x%05X: qprc%02d (Queue Packets Rx Count %02d) 0x%08X\n",
1001 0x01030 + (0x40 * i), i, i, regs_buff[974 + i]);
1002
1003 for (i = 0; i < 16; i++)
1004 fprintf(stdout,
1005 "0x%05X: qptc%02d (Queue Packets Tx Count %02d) 0x%08X\n",
1006 0x06030 + (0x40 * i), i, i, regs_buff[990 + i]);
1007
1008 for (i = 0; i < 16; i++)
1009 fprintf(stdout,
1010 "0x%05X: qbrc%02d (Queue Bytes Rx Count %02d) 0x%08X\n",
1011 0x01034 + (0x40 * i), i, i, regs_buff[1006 + i]);
1012
1013 for (i = 0; i < 16; i++)
1014 fprintf(stdout,
1015 "0x%05X: qbtc%02d (Queue Bytes Tx Count %02d) 0x%08X\n",
1016 0x06034 + (0x40 * i), i, i, regs_buff[1022 + i]);
1017
1018 /* MAC */
1019 if (mac_type < ixgbe_mac_X540) {
1020 fprintf(stdout,
1021 "0x04200: PCS1GCFIG (PCS_1G Gloabal Config 1) 0x%08X\n",
1022 regs_buff[1038]);
1023
1024 fprintf(stdout,
1025 "0x04208: PCS1GLCTL (PCS_1G Link Control) 0x%08X\n",
1026 regs_buff[1039]);
1027
1028 fprintf(stdout,
1029 "0x0420C: PCS1GLSTA (PCS_1G Link Status) 0x%08X\n",
1030 regs_buff[1040]);
1031
1032 fprintf(stdout,
1033 "0x04210: PCS1GDBG0 (PCS_1G Debug 0) 0x%08X\n",
1034 regs_buff[1041]);
1035
1036 fprintf(stdout,
1037 "0x04214: PCS1GDBG1 (PCS_1G Debug 1) 0x%08X\n",
1038 regs_buff[1042]);
1039
1040 fprintf(stdout,
1041 "0x04218: PCS1GANA (PCS-1G Auto Neg. Adv.) 0x%08X\n",
1042 regs_buff[1043]);
1043
1044 fprintf(stdout,
1045 "0x0421C: PCS1GANLP (PCS-1G AN LP Ability) 0x%08X\n",
1046 regs_buff[1044]);
1047
1048 fprintf(stdout,
1049 "0x04220: PCS1GANNP (PCS_1G Auto Neg Next Page Tx) 0x%08X\n",
1050 regs_buff[1045]);
1051
1052 fprintf(stdout,
1053 "0x04224: PCS1GANLPNP (PCS_1G Auto Neg LPs Next Page) 0x%08X\n",
1054 regs_buff[1046]);
1055 }
1056
1057 fprintf(stdout,
1058 "0x04244: HLREG1 (Highlander Status 1) 0x%08X\n",
1059 regs_buff[1048]);
1060
1061 fprintf(stdout,
1062 "0x04248: PAP (Pause and Pace) 0x%08X\n",
1063 regs_buff[1049]);
1064
1065 fprintf(stdout,
1066 "0x0424C: MACA (MDI Auto-Scan Command and Addr) 0x%08X\n",
1067 regs_buff[1050]);
1068
1069 fprintf(stdout,
1070 "0x04250: APAE (Auto-Scan PHY Address Enable) 0x%08X\n",
1071 regs_buff[1051]);
1072
1073 fprintf(stdout,
1074 "0x04254: ARD (Auto-Scan Read Data) 0x%08X\n",
1075 regs_buff[1052]);
1076
1077 fprintf(stdout,
1078 "0x04258: AIS (Auto-Scan Interrupt Status) 0x%08X\n",
1079 regs_buff[1053]);
1080
1081 fprintf(stdout,
1082 "0x0425C: MSCA (MDI Single Command and Addr) 0x%08X\n",
1083 regs_buff[1054]);
1084
1085 fprintf(stdout,
1086 "0x04260: MSRWD (MDI Single Read and Write Data) 0x%08X\n",
1087 regs_buff[1055]);
1088
1089 fprintf(stdout,
1090 "0x04264: MLADD (MAC Address Low) 0x%08X\n",
1091 regs_buff[1056]);
1092
1093 fprintf(stdout,
1094 "0x04268: MHADD (MAC Addr High/Max Frame size) 0x%08X\n",
1095 regs_buff[1057]);
1096
1097 fprintf(stdout,
1098 "0x0426C: TREG (Test Register) 0x%08X\n",
1099 regs_buff[1058]);
1100
1101 if (mac_type < ixgbe_mac_X540) {
1102 fprintf(stdout,
1103 "0x04288: PCSS1 (XGXS Status 1) 0x%08X\n",
1104 regs_buff[1059]);
1105
1106 fprintf(stdout,
1107 "0x0428C: PCSS2 (XGXS Status 2) 0x%08X\n",
1108 regs_buff[1060]);
1109
1110 fprintf(stdout,
1111 "0x04290: XPCSS (10GBASE-X PCS Status) 0x%08X\n",
1112 regs_buff[1061]);
1113
1114 fprintf(stdout,
1115 "0x04298: SERDESC (SERDES Interface Control) 0x%08X\n",
1116 regs_buff[1062]);
1117
1118 fprintf(stdout,
1119 "0x0429C: MACS (FIFO Status/CNTL Report) 0x%08X\n",
1120 regs_buff[1063]);
1121
1122 fprintf(stdout,
1123 "0x042A0: AUTOC (Auto Negotiation Control) 0x%08X\n",
1124 regs_buff[1064]);
1125
1126 fprintf(stdout,
1127 "0x042A8: AUTOC2 (Auto Negotiation Control 2) 0x%08X\n",
1128 regs_buff[1066]);
1129
1130 fprintf(stdout,
1131 "0x042AC: AUTOC3 (Auto Negotiation Control 3) 0x%08X\n",
1132 regs_buff[1067]);
1133
1134 fprintf(stdout,
1135 "0x042B0: ANLP1 (Auto Neg Lnk Part. Ctrl Word 1) 0x%08X\n",
1136 regs_buff[1068]);
1137
1138 fprintf(stdout,
1139 "0x042B4: ANLP2 (Auto Neg Lnk Part. Ctrl Word 2) 0x%08X\n",
1140 regs_buff[1069]);
1141 }
1142
1143 if (mac_type == ixgbe_mac_82598EB) {
1144 fprintf(stdout,
1145 "0x04800: ATLASCTL (Atlas Analog Configuration) 0x%08X\n",
1146 regs_buff[1070]);
1147
1148 /* Diagnostic */
1149 fprintf(stdout,
1150 "0x02C20: RDSTATCTL (Rx DMA Statistic Control) 0x%08X\n",
1151 regs_buff[1071]);
1152
1153 for (i = 0; i < 8; i++)
1154 fprintf(stdout,
1155 "0x%05X: RDSTAT%d (Rx DMA Statistics %d) 0x%08X\n",
1156 0x02C00 + (4 * i), i, i, regs_buff[1072 + i]);
1157
1158 fprintf(stdout,
1159 "0x02F08: RDHMPN (Rx Desc Handler Mem Page num) 0x%08X\n",
1160 regs_buff[1080]);
1161
1162 fprintf(stdout,
1163 "0x02F10: RIC_DW0 (Rx Desc Hand. Mem Read Data 0) 0x%08X\n",
1164 regs_buff[1081]);
1165
1166 fprintf(stdout,
1167 "0x02F14: RIC_DW1 (Rx Desc Hand. Mem Read Data 1) 0x%08X\n",
1168 regs_buff[1082]);
1169
1170 fprintf(stdout,
1171 "0x02F18: RIC_DW2 (Rx Desc Hand. Mem Read Data 2) 0x%08X\n",
1172 regs_buff[1083]);
1173
1174 fprintf(stdout,
1175 "0x02F1C: RIC_DW3 (Rx Desc Hand. Mem Read Data 3) 0x%08X\n",
1176 regs_buff[1084]);
1177 }
1178
1179 if (mac_type < ixgbe_mac_X540)
1180 fprintf(stdout,
1181 "0x02F20: RDPROBE (Rx Probe Mode Status) 0x%08X\n",
1182 regs_buff[1085]);
1183
1184 fprintf(stdout,
1185 "0x07C20: TDSTATCTL (Tx DMA Statistic Control) 0x%08X\n",
1186 regs_buff[1086]);
1187
1188 for (i = 0; i < 8; i++)
1189 fprintf(stdout,
1190 "0x%05X: TDSTAT%d (Tx DMA Statistics %d) 0x%08X\n",
1191 0x07C00 + (4 * i), i, i, regs_buff[1087 + i]);
1192
1193 fprintf(stdout,
1194 "0x07F08: TDHMPN (Tx Desc Handler Mem Page Num) 0x%08X\n",
1195 regs_buff[1095]);
1196
1197 for (i = 0; i < 4; i++)
1198 fprintf(stdout,
1199 "0x%05X: TIC_DW%d (Tx Desc Hand. Mem Read Data %d) 0x%08X\n",
1200 0x07F10 + (4 * i), i, i, regs_buff[1096 + i]);
1201
1202 fprintf(stdout,
1203 "0x07F20: TDPROBE (Tx Probe Mode Status) 0x%08X\n",
1204 regs_buff[1100]);
1205
1206 fprintf(stdout,
1207 "0x0C600: TXBUFCTRL (TX Buffer Access Control) 0x%08X\n",
1208 regs_buff[1101]);
1209
1210 for (i = 0; i < 4; i++)
1211 fprintf(stdout,
1212 "0x%05X: TXBUFDATA%d (TX Buffer DATA %d) 0x%08X\n",
1213 0x0C610 + (4 * i), i, i, regs_buff[1102 + i]);
1214
1215 fprintf(stdout,
1216 "0x03600: RXBUFCTRL (RX Buffer Access Control) 0x%08X\n",
1217 regs_buff[1106]);
1218
1219 for (i = 0; i < 4; i++)
1220 fprintf(stdout,
1221 "0x%05X: RXBUFDATA%d (RX Buffer DATA %d) 0x%08X\n",
1222 0x03610 + (4 * i), i, i, regs_buff[1107 + i]);
1223
1224 for (i = 0; i < 8; i++)
1225 fprintf(stdout,
1226 "0x%05X: PCIE_DIAG%d (PCIe Diagnostic %d) 0x%08X\n",
1227 0x11090 + (4 * i), i, i, regs_buff[1111 + i]);
1228
1229 fprintf(stdout,
1230 "0x050A4: RFVAL (Receive Filter Validation) 0x%08X\n",
1231 regs_buff[1119]);
1232
1233 if (mac_type < ixgbe_mac_X540) {
1234 fprintf(stdout,
1235 "0x042B8: MDFTC1 (MAC DFT Control 1) 0x%08X\n",
1236 regs_buff[1120]);
1237
1238 fprintf(stdout,
1239 "0x042C0: MDFTC2 (MAC DFT Control 2) 0x%08X\n",
1240 regs_buff[1121]);
1241
1242 fprintf(stdout,
1243 "0x042C4: MDFTFIFO1 (MAC DFT FIFO 1) 0x%08X\n",
1244 regs_buff[1122]);
1245
1246 fprintf(stdout,
1247 "0x042C8: MDFTFIFO2 (MAC DFT FIFO 2) 0x%08X\n",
1248 regs_buff[1123]);
1249
1250 fprintf(stdout,
1251 "0x042CC: MDFTS (MAC DFT Status) 0x%08X\n",
1252 regs_buff[1124]);
1253 }
1254
1255 if (mac_type == ixgbe_mac_82598EB) {
1256 fprintf(stdout,
1257 "0x1106C: PCIEECCCTL (PCIe ECC Control) 0x%08X\n",
1258 regs_buff[1125]);
1259
1260 fprintf(stdout,
1261 "0x0C300: PBTXECC (Packet Buffer Tx ECC) 0x%08X\n",
1262 regs_buff[1126]);
1263
1264 fprintf(stdout,
1265 "0x03300: PBRXECC (Packet Buffer Rx ECC) 0x%08X\n",
1266 regs_buff[1127]);
1267 }
1268
1269 if (regs_buff_len > 1139 && mac_type != ixgbe_mac_82598EB) {
1270 fprintf(stdout,
1271 "0x08800: SECTXCTRL (Security Tx Control) 0x%08X\n",
1272 regs_buff[1139]);
1273
1274 fprintf(stdout,
1275 "0x08804: SECTXSTAT (Security Tx Status) 0x%08X\n",
1276 regs_buff[1140]);
1277
1278 fprintf(stdout,
1279 "0x08808: SECTXBUFFAF (Security Tx Buffer Almost Full) 0x%08X\n",
1280 regs_buff[1141]);
1281
1282 fprintf(stdout,
1283 "0x08800: SECTXMINIFG (Security Tx Buffer Minimum IFG) 0x%08X\n",
1284 regs_buff[1142]);
1285
1286 fprintf(stdout,
1287 "0x08800: SECRXCTRL (Security Rx Control) 0x%08X\n",
1288 regs_buff[1143]);
1289
1290 fprintf(stdout,
1291 "0x08800: SECRXSTAT (Security Rx Status) 0x%08X\n",
1292 regs_buff[1144]);
1293 }
1294
1295 return 0;
1296 }
1297