1 /* Copyright (c) 2006 Intel Corporation */
2 #include <stdio.h>
3 #include "internal.h"
4
5 /* CTRL0 Bit Masks */
6 #define IXGB_CTRL0_LRST 0x00000008
7 #define IXGB_CTRL0_VME 0x40000000
8
9 /* STATUS Bit Masks */
10 #define IXGB_STATUS_LU 0x00000002
11 #define IXGB_STATUS_BUS64 0x00001000
12 #define IXGB_STATUS_PCIX_MODE 0x00002000
13 #define IXGB_STATUS_PCIX_SPD_100 0x00004000
14 #define IXGB_STATUS_PCIX_SPD_133 0x00008000
15
16 /* RCTL Bit Masks */
17 #define IXGB_RCTL_RXEN 0x00000002
18 #define IXGB_RCTL_SBP 0x00000004
19 #define IXGB_RCTL_UPE 0x00000008
20 #define IXGB_RCTL_MPE 0x00000010
21 #define IXGB_RCTL_RDMTS_MASK 0x00000300
22 #define IXGB_RCTL_RDMTS_1_2 0x00000000
23 #define IXGB_RCTL_RDMTS_1_4 0x00000100
24 #define IXGB_RCTL_RDMTS_1_8 0x00000200
25 #define IXGB_RCTL_BAM 0x00008000
26 #define IXGB_RCTL_BSIZE_MASK 0x00030000
27 #define IXGB_RCTL_BSIZE_4096 0x00010000
28 #define IXGB_RCTL_BSIZE_8192 0x00020000
29 #define IXGB_RCTL_BSIZE_16384 0x00030000
30 #define IXGB_RCTL_VFE 0x00040000
31 #define IXGB_RCTL_CFIEN 0x00080000
32
33 /* TCTL Bit Masks */
34 #define IXGB_TCTL_TXEN 0x00000002
35
36 /* RAH Bit Masks */
37 #define IXGB_RAH_ASEL_DEST 0x00000000
38 #define IXGB_RAH_ASEL_SRC 0x00010000
39 #define IXGB_RAH_AV 0x80000000
40
ixgb_dump_regs(struct ethtool_drvinfo * info maybe_unused,struct ethtool_regs * regs)41 int ixgb_dump_regs(struct ethtool_drvinfo *info maybe_unused,
42 struct ethtool_regs *regs)
43 {
44 u32 *regs_buff = (u32 *)regs->data;
45 u8 version = (u8)(regs->version >> 24);
46 u32 reg;
47
48 if (version != 1)
49 return -1;
50 fprintf(stdout, "MAC Registers\n");
51 fprintf(stdout, "-------------\n");
52
53 /* Device control register */
54 reg = regs_buff[0];
55 fprintf(stdout,
56 "0x00000: CTRL0 (Device control register) 0x%08X\n"
57 " Link reset: %s\n"
58 " VLAN mode: %s\n",
59 reg,
60 reg & IXGB_CTRL0_LRST ? "reset" : "normal",
61 reg & IXGB_CTRL0_VME ? "enabled" : "disabled");
62
63 /* Device status register */
64 reg = regs_buff[2];
65 fprintf(stdout,
66 "0x00010: STATUS (Device status register) 0x%08X\n"
67 " Link up: %s\n"
68 " Bus type: %s\n"
69 " Bus speed: %s\n"
70 " Bus width: %s\n",
71 reg,
72 (reg & IXGB_STATUS_LU) ? "link config" : "no link config",
73 (reg & IXGB_STATUS_PCIX_MODE) ? "PCI-X" : "PCI",
74 ((reg & IXGB_STATUS_PCIX_SPD_133) ? "133MHz" :
75 (reg & IXGB_STATUS_PCIX_SPD_100) ? "100MHz" :
76 "66MHz"),
77 (reg & IXGB_STATUS_BUS64) ? "64-bit" : "32-bit");
78 /* Receive control register */
79 reg = regs_buff[9];
80 fprintf(stdout,
81 "0x00100: RCTL (Receive control register) 0x%08X\n"
82 " Receiver: %s\n"
83 " Store bad packets: %s\n"
84 " Unicast promiscuous: %s\n"
85 " Multicast promiscuous: %s\n"
86 " Descriptor minimum threshold size: %s\n"
87 " Broadcast accept mode: %s\n"
88 " VLAN filter: %s\n"
89 " Cononical form indicator: %s\n",
90 reg,
91 reg & IXGB_RCTL_RXEN ? "enabled" : "disabled",
92 reg & IXGB_RCTL_SBP ? "enabled" : "disabled",
93 reg & IXGB_RCTL_UPE ? "enabled" : "disabled",
94 reg & IXGB_RCTL_MPE ? "enabled" : "disabled",
95 (reg & IXGB_RCTL_RDMTS_MASK) == IXGB_RCTL_RDMTS_1_2 ? "1/2" :
96 (reg & IXGB_RCTL_RDMTS_MASK) == IXGB_RCTL_RDMTS_1_4 ? "1/4" :
97 (reg & IXGB_RCTL_RDMTS_MASK) == IXGB_RCTL_RDMTS_1_8 ? "1/8" :
98 "reserved",
99 reg & IXGB_RCTL_BAM ? "accept" : "ignore",
100 reg & IXGB_RCTL_VFE ? "enabled" : "disabled",
101 reg & IXGB_RCTL_CFIEN ? "enabled" : "disabled");
102 fprintf(stdout,
103 " Receive buffer size: %s\n",
104 (reg & IXGB_RCTL_BSIZE_MASK) == IXGB_RCTL_BSIZE_16384 ? "16384" :
105 (reg & IXGB_RCTL_BSIZE_MASK) == IXGB_RCTL_BSIZE_8192 ? "8192" :
106 (reg & IXGB_RCTL_BSIZE_MASK) == IXGB_RCTL_BSIZE_4096 ? "4096" :
107 "2048");
108
109 /* Receive descriptor registers */
110 fprintf(stdout,
111 "0x00120: RDLEN (Receive desc length) 0x%08X\n",
112 regs_buff[14]);
113 fprintf(stdout,
114 "0x00128: RDH (Receive desc head) 0x%08X\n",
115 regs_buff[15]);
116 fprintf(stdout,
117 "0x00130: RDT (Receive desc tail) 0x%08X\n",
118 regs_buff[16]);
119 fprintf(stdout,
120 "0x00138: RDTR (Receive delay timer) 0x%08X\n",
121 regs_buff[17]);
122
123 /* Transmit control register */
124 reg = regs_buff[53];
125 fprintf(stdout,
126 "0x00600: TCTL (Transmit ctrl register) 0x%08X\n"
127 " Transmitter: %s\n",
128 reg,
129 reg & IXGB_TCTL_TXEN ? "enabled" : "disabled");
130
131 /* Transmit descriptor registers */
132 fprintf(stdout,
133 "0x00610: TDLEN (Transmit desc length) 0x%08X\n",
134 regs_buff[56]);
135 fprintf(stdout,
136 "0x00618: TDH (Transmit desc head) 0x%08X\n",
137 regs_buff[57]);
138 fprintf(stdout,
139 "0x00620: TDT (Transmit desc tail) 0x%08X\n",
140 regs_buff[58]);
141 fprintf(stdout,
142 "0x00628: TIDV (Transmit delay timer) 0x%08X\n",
143 regs_buff[59]);
144
145 return 0;
146 }
147
148