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Searched refs:ImplicitDefs (Results 1 – 25 of 51) sorted by relevance

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/external/llvm/include/llvm/MC/
DMCInstrDesc.h148 const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr variable
497 const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; } in getImplicitDefs()
501 if (!ImplicitDefs) in getNumImplicitDefs()
504 for (; ImplicitDefs[i]; ++i) /*empty*/ in getNumImplicitDefs()
/external/llvm-project/llvm/include/llvm/MC/
DMCInstrDesc.h197 const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr variable
573 const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; } in getImplicitDefs()
577 if (!ImplicitDefs) in getNumImplicitDefs()
580 for (; ImplicitDefs[i]; ++i) /*empty*/ in getNumImplicitDefs()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/
DMCInstrDesc.h198 const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr variable
588 const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; } in getImplicitDefs()
592 if (!ImplicitDefs) in getNumImplicitDefs()
595 for (; ImplicitDefs[i]; ++i) /*empty*/ in getNumImplicitDefs()
/external/llvm/lib/CodeGen/
DMachineCSE.cpp455 SmallVector<unsigned, 2> ImplicitDefs; in ProcessBlock() local
550 ImplicitDefs.push_back(OldReg); in ProcessBlock()
611 for (auto ImplicitDef : ImplicitDefs) in ProcessBlock()
618 for (auto ImplicitDef : ImplicitDefs) in ProcessBlock()
646 ImplicitDefs.clear(); in ProcessBlock()
/external/llvm-project/llvm/utils/TableGen/
DInstrDocsEmitter.cpp193 if (!II->ImplicitDefs.empty()) { in EmitInstrDocs()
196 for (Record *Def : II->ImplicitDefs) { in EmitInstrDocs()
DCodeGenInstruction.cpp422 ImplicitDefs = R->getValueAsListOfDefs("Defs"); in CodeGenInstruction()
458 if (ImplicitDefs.empty()) return MVT::Other; in HasOneImplicitDefWithKnownVT()
461 Record *FirstImplicitDef = ImplicitDefs[0]; in HasOneImplicitDefWithKnownVT()
DCodeGenInstruction.h233 std::vector<Record*> ImplicitDefs, ImplicitUses; variable
DDAGISelMatcherGen.cpp921 HandledReg = II.ImplicitDefs[0]; in EmitResultInstructionAsOperand()
1063 HandledReg = II.ImplicitDefs[0]; in EmitResultCode()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DMachineCSE.cpp516 SmallVector<unsigned, 2> ImplicitDefs; in ProcessBlockCSE() local
610 ImplicitDefs.push_back(OldReg); in ProcessBlockCSE()
675 for (auto ImplicitDef : ImplicitDefs) in ProcessBlockCSE()
682 for (auto ImplicitDef : ImplicitDefs) in ProcessBlockCSE()
710 ImplicitDefs.clear(); in ProcessBlockCSE()
/external/llvm-project/llvm/lib/CodeGen/
DMachineCSE.cpp516 SmallVector<unsigned, 2> ImplicitDefs; in ProcessBlockCSE() local
610 ImplicitDefs.push_back(OldReg); in ProcessBlockCSE()
675 for (auto ImplicitDef : ImplicitDefs) in ProcessBlockCSE()
682 for (auto ImplicitDef : ImplicitDefs) in ProcessBlockCSE()
710 ImplicitDefs.clear(); in ProcessBlockCSE()
/external/capstone/
DMCInstrDesc.h131 char ImplicitDefs; // Registers implicitly defined by this instr member
/external/llvm-project/llvm/lib/MC/
DMCInstrDesc.cpp35 if (const MCPhysReg *ImpDefs = ImplicitDefs) in hasImplicitDefOfPhysReg()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/MC/
DMCInstrDesc.cpp46 if (const MCPhysReg *ImpDefs = ImplicitDefs) in hasImplicitDefOfPhysReg()
/external/llvm/lib/MC/
DMCInstrDesc.cpp56 if (const MCPhysReg *ImpDefs = ImplicitDefs) in hasImplicitDefOfPhysReg()
/external/llvm/utils/TableGen/
DCodeGenInstruction.cpp342 ImplicitDefs = R->getValueAsListOfDefs("Defs"); in CodeGenInstruction()
371 if (ImplicitDefs.empty()) return MVT::Other; in HasOneImplicitDefWithKnownVT()
374 Record *FirstImplicitDef = ImplicitDefs[0]; in HasOneImplicitDefWithKnownVT()
DCodeGenInstruction.h221 std::vector<Record*> ImplicitDefs, ImplicitUses; variable
DDAGISelMatcherGen.cpp849 HandledReg = II.ImplicitDefs[0]; in EmitResultInstructionAsOperand()
972 HandledReg = II.ImplicitDefs[0]; in EmitResultCode()
/external/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp1830 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_r()
1855 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rr()
1883 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rrr()
1905 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_ri()
1930 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rii()
1949 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_f()
1975 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rri()
1991 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_i()
DScheduleDAGFast.cpp441 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
520 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp2129 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_r()
2154 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rr()
2182 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rrr()
2204 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_ri()
2229 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rii()
2248 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_f()
2274 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rri()
2290 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_i()
DScheduleDAGFast.cpp433 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
512 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp2064 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_r()
2089 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rr()
2117 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rrr()
2139 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_ri()
2164 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rii()
2183 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_f()
2209 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rri()
2225 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_i()
DScheduleDAGFast.cpp433 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
512 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
/external/llvm/lib/Target/Hexagon/
DHexagonGenMux.cpp127 if (const MCPhysReg *R = D.ImplicitDefs) in getDefsUses()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonGenMux.cpp163 if (const MCPhysReg *R = D.ImplicitDefs) in getDefsUses()

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