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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMicroMipsInstrFormats.td1 //===-- MicroMipsInstrFormats.td - microMIPS Inst Formats -*- tablegen -*--===//
47 field bits<16> Inst;
61 bits<16> Inst;
63 let Inst{15-10} = 0x01;
64 let Inst{9-7} = rd;
65 let Inst{6-4} = rt;
66 let Inst{3-1} = rs;
67 let Inst{0} = funct;
75 bits<16> Inst;
77 let Inst{15-10} = funct;
[all …]
DMicroMips32r6InstrFormats.td40 bits<16> Inst;
42 let Inst{15-10} = 0x33;
43 let Inst{9-0} = offset;
50 bits<16> Inst;
52 let Inst{15-10} = op;
53 let Inst{9-7} = rs;
54 let Inst{6-0} = offset;
60 bits<16> Inst;
62 let Inst{15-10} = 0x11;
63 let Inst{9-5} = rs;
[all …]
DMipsInstrFormats.td74 field bits<32> Inst;
84 let Inst{31-26} = Opcode;
164 let Inst{25-21} = rs;
165 let Inst{20-16} = rt;
166 let Inst{15-11} = rd;
167 let Inst{10-6} = shamt;
168 let Inst{5-0} = funct;
184 let Inst{25-21} = rs;
185 let Inst{20-16} = rt;
186 let Inst{15-0} = imm16;
[all …]
DMipsMSAInstrFormats.td12 let Inst{31-26} = 0b011110;
16 let Inst{31-26} = 0b010001;
20 let Inst{31-26} = 0b000000;
35 let Inst{25-23} = major;
36 let Inst{22-19} = 0b1110;
37 let Inst{18-16} = m;
38 let Inst{15-11} = ws;
39 let Inst{10-6} = wd;
40 let Inst{5-0} = minor;
48 let Inst{25-23} = major;
[all …]
DMicroMipsDSPInstrFormats.td29 let Inst{31-26} = 0b000000;
30 let Inst{25-21} = rt;
31 let Inst{20-16} = rs;
32 let Inst{15-11} = rd;
33 let Inst{10-0} = op;
40 let Inst{31-26} = 0b000000;
41 let Inst{25-21} = rt;
42 let Inst{20-16} = rs;
43 let Inst{15-6} = op;
44 let Inst{5-0} = 0b111100;
[all …]
/external/llvm-project/llvm/lib/Target/Mips/
DMicroMipsInstrFormats.td1 //===-- MicroMipsInstrFormats.td - microMIPS Inst Formats -*- tablegen -*--===//
47 field bits<16> Inst;
61 bits<16> Inst;
63 let Inst{15-10} = 0x01;
64 let Inst{9-7} = rd;
65 let Inst{6-4} = rt;
66 let Inst{3-1} = rs;
67 let Inst{0} = funct;
75 bits<16> Inst;
77 let Inst{15-10} = funct;
[all …]
DMicroMips32r6InstrFormats.td40 bits<16> Inst;
42 let Inst{15-10} = 0x33;
43 let Inst{9-0} = offset;
50 bits<16> Inst;
52 let Inst{15-10} = op;
53 let Inst{9-7} = rs;
54 let Inst{6-0} = offset;
60 bits<16> Inst;
62 let Inst{15-10} = 0x11;
63 let Inst{9-5} = rs;
[all …]
DMipsMSAInstrFormats.td12 let Inst{31-26} = 0b011110;
16 let Inst{31-26} = 0b010001;
20 let Inst{31-26} = 0b000000;
35 let Inst{25-23} = major;
36 let Inst{22-19} = 0b1110;
37 let Inst{18-16} = m;
38 let Inst{15-11} = ws;
39 let Inst{10-6} = wd;
40 let Inst{5-0} = minor;
48 let Inst{25-23} = major;
[all …]
DMipsInstrFormats.td74 field bits<32> Inst;
84 let Inst{31-26} = Opcode;
164 let Inst{25-21} = rs;
165 let Inst{20-16} = rt;
166 let Inst{15-11} = rd;
167 let Inst{10-6} = shamt;
168 let Inst{5-0} = funct;
179 bits<32> Inst;
181 let Inst{31-26} = op;
182 let Inst{25-0} = target;
[all …]
DMicroMipsDSPInstrFormats.td29 let Inst{31-26} = 0b000000;
30 let Inst{25-21} = rt;
31 let Inst{20-16} = rs;
32 let Inst{15-11} = rd;
33 let Inst{10-0} = op;
40 let Inst{31-26} = 0b000000;
41 let Inst{25-21} = rt;
42 let Inst{20-16} = rs;
43 let Inst{15-6} = op;
44 let Inst{5-0} = 0b111100;
[all …]
/external/llvm/lib/Target/Mips/
DMicroMips32r6InstrFormats.td47 bits<16> Inst;
49 let Inst{15-10} = 0x33;
50 let Inst{9-0} = offset;
57 bits<16> Inst;
59 let Inst{15-10} = op;
60 let Inst{9-7} = rs;
61 let Inst{6-0} = offset;
67 bits<16> Inst;
69 let Inst{15-10} = 0x11;
70 let Inst{9-5} = rs;
[all …]
DMicroMipsInstrFormats.td35 field bits<16> Inst;
49 bits<16> Inst;
51 let Inst{15-10} = 0x01;
52 let Inst{9-7} = rd;
53 let Inst{6-4} = rt;
54 let Inst{3-1} = rs;
55 let Inst{0} = funct;
63 bits<16> Inst;
65 let Inst{15-10} = funct;
66 let Inst{9-7} = rd;
[all …]
DMipsMSAInstrFormats.td13 let Inst{31-26} = 0b011110;
17 let Inst{31-26} = 0b010001;
21 let Inst{31-26} = 0b000000;
35 let Inst{25-23} = major;
36 let Inst{22-19} = 0b1110;
37 let Inst{18-16} = m;
38 let Inst{15-11} = ws;
39 let Inst{10-6} = wd;
40 let Inst{5-0} = minor;
48 let Inst{25-23} = major;
[all …]
DMipsInstrFormats.td75 field bits<32> Inst;
85 let Inst{31-26} = Opcode;
161 let Inst{25-21} = rs;
162 let Inst{20-16} = rt;
163 let Inst{15-11} = rd;
164 let Inst{10-6} = shamt;
165 let Inst{5-0} = funct;
181 let Inst{25-21} = rs;
182 let Inst{20-16} = rt;
183 let Inst{15-0} = imm16;
[all …]
DMicroMipsDSPInstrFormats.td30 let Inst{31-26} = 0b000000;
31 let Inst{25-21} = rt;
32 let Inst{20-16} = rs;
33 let Inst{15-11} = rd;
34 let Inst{10-0} = op;
41 let Inst{31-26} = 0b000000;
42 let Inst{25-21} = rt;
43 let Inst{20-16} = rs;
44 let Inst{15-6} = op;
45 let Inst{5-0} = 0b111100;
[all …]
DMicroMips64r6InstrFormats.td19 bits<32> Inst;
21 let Inst{31-26} = 0b111100;
22 let Inst{25-21} = rt;
23 let Inst{20-16} = rs;
24 let Inst{15-0} = imm;
31 bits<32> Inst;
33 let Inst{31-26} = 0b010000;
34 let Inst{25-21} = funct;
35 let Inst{20-16} = rs;
36 let Inst{15-0} = imm;
[all …]
DMips32r6InstrFormats.td181 bits<32> Inst;
183 let Inst{31-26} = OPGROUP_AUI.Value;
184 let Inst{25-21} = rs;
185 let Inst{20-16} = rt;
186 let Inst{15-0} = imm;
190 let Inst{31-26} = OPGROUP_DAUI.Value;
196 bits<32> Inst;
198 let Inst{31-26} = OPGROUP_REGIMM.Value;
199 let Inst{25-21} = 0b00000;
200 let Inst{20-16} = OPCODE5_BGEZAL.Value;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonDepInstrFormats.td13 let Inst{20-16} = Rs32{4-0};
15 let Inst{4-0} = Rd32{4-0};
17 let Inst{6-5} = Pe4{1-0};
21 let Inst{6-5} = Qs4{1-0};
23 let Inst{20-16} = Rt32{4-0};
25 let Inst{13-13} = Mu2{0-0};
27 let Inst{12-8} = Vv32{4-0};
29 let Inst{4-0} = Vw32{4-0};
33 let Inst{17-16} = Ps4{1-0};
35 let Inst{9-8} = Pt4{1-0};
[all …]
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonDepInstrFormats.td13 let Inst{20-16} = Rs32{4-0};
15 let Inst{4-0} = Rd32{4-0};
19 let Inst{20-16} = Rss32{4-0};
21 let Inst{4-0} = Rdd32{4-0};
25 let Inst{20-16} = Rs32{4-0};
27 let Inst{12-8} = Rt32{4-0};
29 let Inst{4-0} = Rd32{4-0};
33 let Inst{12-8} = Rt32{4-0};
35 let Inst{20-16} = Rs32{4-0};
37 let Inst{4-0} = Rd32{4-0};
[all …]
/external/capstone/arch/XCore/
DXCoreDisassembler.c66 static DecodeStatus DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
69 static DecodeStatus DecodeRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
72 static DecodeStatus DecodeBitpOperand(MCInst *Inst, unsigned Val,
75 static DecodeStatus DecodeNegImmOperand(MCInst *Inst, unsigned Val,
78 static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn,
81 static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn,
84 static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn,
87 static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn,
90 static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn,
93 static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn,
[all …]
/external/llvm/lib/Target/AMDGPU/
DVIInstrFormats.td23 let Inst{7-0} = offset0;
24 let Inst{15-8} = offset1;
25 let Inst{16} = gds;
26 let Inst{24-17} = op;
27 let Inst{31-26} = 0x36; //encoding
28 let Inst{39-32} = addr;
29 let Inst{47-40} = data0;
30 let Inst{55-48} = data1;
31 let Inst{63-56} = vdst;
47 let Inst{11-0} = offset;
[all …]
/external/capstone/arch/SystemZ/
DSystemZDisassembler.c39 static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo, const unsigned *Regs) in decodeRegisterClass() argument
46 MCOperand_CreateReg0(Inst, (unsigned)RegNo); in decodeRegisterClass()
50 static DecodeStatus DecodeGR32BitRegisterClass(MCInst *Inst, uint64_t RegNo, in DecodeGR32BitRegisterClass() argument
53 return decodeRegisterClass(Inst, RegNo, SystemZMC_GR32Regs); in DecodeGR32BitRegisterClass()
56 static DecodeStatus DecodeGRH32BitRegisterClass(MCInst *Inst, uint64_t RegNo, in DecodeGRH32BitRegisterClass() argument
59 return decodeRegisterClass(Inst, RegNo, SystemZMC_GRH32Regs); in DecodeGRH32BitRegisterClass()
62 static DecodeStatus DecodeGR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, in DecodeGR64BitRegisterClass() argument
65 return decodeRegisterClass(Inst, RegNo, SystemZMC_GR64Regs); in DecodeGR64BitRegisterClass()
68 static DecodeStatus DecodeGR128BitRegisterClass(MCInst *Inst, uint64_t RegNo, in DecodeGR128BitRegisterClass() argument
71 return decodeRegisterClass(Inst, RegNo, SystemZMC_GR128Regs); in DecodeGR128BitRegisterClass()
[all …]
/external/llvm/lib/Target/XCore/Disassembler/
DXCoreDisassembler.cpp76 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
81 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
86 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
89 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
92 static DecodeStatus Decode2RInstruction(MCInst &Inst,
97 static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
102 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
107 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
112 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
117 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/Disassembler/
DXCoreDisassembler.cpp75 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
80 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
85 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
88 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
91 static DecodeStatus Decode2RInstruction(MCInst &Inst,
96 static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
101 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
106 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
111 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
116 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
[all …]
/external/llvm-project/llvm/lib/Target/XCore/Disassembler/
DXCoreDisassembler.cpp75 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
80 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
85 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
88 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
91 static DecodeStatus Decode2RInstruction(MCInst &Inst,
96 static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
101 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
106 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
111 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
116 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
[all …]

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