| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsRegisterBankInfo.h | 56 enum InstType { enum
75 bool isAmbiguous_64(InstType InstTy, unsigned OpSize) const { in isAmbiguous_64()
76 if (InstTy == InstType::Ambiguous && OpSize == 64) in isAmbiguous_64()
81 bool isAmbiguous_32(InstType InstTy, unsigned OpSize) const { in isAmbiguous_32()
82 if (InstTy == InstType::Ambiguous && OpSize == 32) in isAmbiguous_32()
87 bool isAmbiguous_32or64(InstType InstTy, unsigned OpSize) const { in isAmbiguous_32or64()
88 if (InstTy == InstType::Ambiguous && (OpSize == 32 || OpSize == 64)) in isAmbiguous_32or64()
93 bool isAmbiguousWithMergeOrUnmerge_64(InstType InstTy, in isAmbiguousWithMergeOrUnmerge_64()
95 if (InstTy == InstType::AmbiguousWithMergeOrUnmerge && OpSize == 64) in isAmbiguousWithMergeOrUnmerge_64()
100 bool isFloatingPoint_32or64(InstType InstTy, unsigned OpSize) const { in isFloatingPoint_32or64()
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| D | MipsRegisterBankInfo.cpp | 269 InstType &AmbiguousTy) { in visit()
282 if (AmbiguousTy == InstType::Ambiguous && in visit()
285 AmbiguousTy = InstType::AmbiguousWithMergeOrUnmerge; in visit()
315 bool isDefUse, InstType &AmbiguousTy) { in visitAdjacentInstrs()
321 setTypes(MI, InstType::FloatingPoint); in visitAdjacentInstrs()
337 setTypes(MI, InstType::Integer); in visitAdjacentInstrs()
344 getRecordedTypeForInstr(AdjMI) != InstType::NotDetermined) { in visitAdjacentInstrs()
356 InstType InstTy) { in setTypes()
377 setTypes(MI, InstType::FloatingPoint); in setTypesAccordingToPhysicalRegister()
379 setTypes(MI, InstType::Integer); in setTypesAccordingToPhysicalRegister()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsRegisterBankInfo.h | 56 enum InstType { enum
113 DenseMap<const MachineInstr *, InstType> Types;
125 void setTypes(const MachineInstr *MI, InstType ITy);
135 Types.try_emplace(MI, InstType::NotDetermined); in startVisit()
144 const InstType &getRecordedTypeForInstr(const MachineInstr *MI) const { in getRecordedTypeForInstr()
150 void changeRecordedTypeForInstr(const MachineInstr *MI, InstType InstTy) { in changeRecordedTypeForInstr()
170 InstType determineInstType(const MachineInstr *MI);
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| D | MipsRegisterBankInfo.cpp | 272 setTypes(MI, InstType::Ambiguous); in visit()
295 setTypes(MI, InstType::FloatingPoint); in visitAdjacentInstrs()
309 setTypes(MI, InstType::Integer); in visitAdjacentInstrs()
316 getRecordedTypeForInstr(AdjMI) != InstType::NotDetermined) { in visitAdjacentInstrs()
328 InstType InstTy) { in setTypes()
349 setTypes(MI, InstType::FloatingPoint); in setTypesAccordingToPhysicalRegister()
351 setTypes(MI, InstType::Integer); in setTypesAccordingToPhysicalRegister()
356 MipsRegisterBankInfo::InstType
437 InstType InstTy = InstType::Integer; in getInstrMapping()
480 if (InstTy == InstType::FloatingPoint || in getInstrMapping()
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| /external/eigen/unsupported/Eigen/CXX11/src/util/ |
| D | CXX11Meta.h | 485 template<class InstType, typename ArrType, std::size_t N, bool Reverse, typename... Ps>
488 template<class InstType, typename ArrType, std::size_t N, typename... Ps>
489 struct h_instantiate_by_c_array<InstType, ArrType, N, false, Ps...>
491 static InstType run(ArrType* arr, Ps... args)
493 …return h_instantiate_by_c_array<InstType, ArrType, N - 1, false, Ps..., ArrType>::run(arr + 1, arg…
497 template<class InstType, typename ArrType, std::size_t N, typename... Ps>
498 struct h_instantiate_by_c_array<InstType, ArrType, N, true, Ps...>
500 static InstType run(ArrType* arr, Ps... args)
502 …return h_instantiate_by_c_array<InstType, ArrType, N - 1, false, ArrType, Ps...>::run(arr + 1, arr…
506 template<class InstType, typename ArrType, typename... Ps>
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNHazardRecognizer.cpp | 1086 auto InstType = IsHazardInst(MI); in fixLdsBranchVmemWARHazard() local
1087 if (!InstType) in fixLdsBranchVmemWARHazard()
1097 auto IsHazardFn = [InstType, &IsHazardInst] (MachineInstr *I) { in fixLdsBranchVmemWARHazard()
1101 auto IsHazardFn = [InstType, IsHazardInst] (MachineInstr *I) { in fixLdsBranchVmemWARHazard()
1103 return InstType2 && InstType != InstType2; in fixLdsBranchVmemWARHazard()
1106 auto IsExpiredFn = [InstType, &IsHazardInst] (MachineInstr *I, int) { in fixLdsBranchVmemWARHazard()
1111 if (InstType == InstType2) in fixLdsBranchVmemWARHazard()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | GCNHazardRecognizer.cpp | 1090 auto InstType = IsHazardInst(MI); in fixLdsBranchVmemWARHazard() local
1091 if (!InstType) in fixLdsBranchVmemWARHazard()
1101 auto IsHazardFn = [InstType, &IsHazardInst] (MachineInstr *I) { in fixLdsBranchVmemWARHazard()
1105 auto IsHazardFn = [InstType, IsHazardInst] (MachineInstr *I) { in fixLdsBranchVmemWARHazard()
1107 return InstType2 && InstType != InstType2; in fixLdsBranchVmemWARHazard()
1110 auto IsExpiredFn = [InstType, &IsHazardInst] (MachineInstr *I, int) { in fixLdsBranchVmemWARHazard()
1115 if (InstType == InstType2) in fixLdsBranchVmemWARHazard()
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| /external/llvm-project/llvm/lib/Target/VE/ |
| D | VEInstrInfo.cpp | 595 enum InstType { in FoldImmediate() enum
598 } InstType; in FoldImmediate() local
605 InstType = rr2ri_rm; \ in FoldImmediate()
611 InstType = rr2ir_rm; \ in FoldImmediate()
658 switch (InstType) { in FoldImmediate()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInsertWaits.cpp | 50 } InstType; typedef
89 InstType LastOpcodeType;
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerARM32.h | 723 void emitType01(CondARM32::Cond Cond, IValueT InstType, IValueT Opcode,
745 void emitMemOp(CondARM32::Cond Cond, IValueT InstType, bool IsLoad,
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| D | IceAssemblerARM32.cpp | 797 void AssemblerARM32::emitType01(CondARM32::Cond Cond, IValueT InstType, in emitType01() argument
811 (InstType << kTypeShift) | (Opcode << kOpcodeShift) | in emitType01()
936 void AssemblerARM32::emitMemOp(CondARM32::Cond Cond, IValueT InstType, in emitMemOp() argument
942 (InstType << kTypeShift) | (IsLoad ? L : 0) | in emitMemOp()
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