| /external/swiftshader/third_party/subzero/src/ |
| D | IceConverter.cpp | 206 Ice::Operand *convertOperand(const Instruction *Instr, unsigned OpNum) { in convertOperand() argument
207 if (OpNum >= Instr->getNumOperands()) { in convertOperand()
210 const Value *Op = Instr->getOperand(OpNum); in convertOperand()
224 Ice::Inst *convertInstruction(const Instruction *Instr) { in convertInstruction() argument
225 switch (Instr->getOpcode()) { in convertInstruction()
227 return convertPHINodeInstruction(cast<PHINode>(Instr)); in convertInstruction()
229 return convertBrInstruction(cast<BranchInst>(Instr)); in convertInstruction()
231 return convertRetInstruction(cast<ReturnInst>(Instr)); in convertInstruction()
233 return convertIntToPtrInstruction(cast<IntToPtrInst>(Instr)); in convertInstruction()
235 return convertPtrToIntInstruction(cast<PtrToIntInst>(Instr)); in convertInstruction()
[all …]
|
| D | IceInstrumentation.cpp | 61 Inst *Instr = iteratorToInst(Context.getCur()); in instrumentInst() local
62 switch (Instr->getKind()) { in instrumentInst()
64 instrumentAlloca(Context, llvm::cast<InstAlloca>(Instr)); in instrumentInst()
67 instrumentArithmetic(Context, llvm::cast<InstArithmetic>(Instr)); in instrumentInst()
70 instrumentBr(Context, llvm::cast<InstBr>(Instr)); in instrumentInst()
73 instrumentCall(Context, llvm::cast<InstCall>(Instr)); in instrumentInst()
76 instrumentCast(Context, llvm::cast<InstCast>(Instr)); in instrumentInst()
79 instrumentExtractElement(Context, llvm::cast<InstExtractElement>(Instr)); in instrumentInst()
82 instrumentFcmp(Context, llvm::cast<InstFcmp>(Instr)); in instrumentInst()
85 instrumentIcmp(Context, llvm::cast<InstIcmp>(Instr)); in instrumentInst()
[all …]
|
| D | IceVariableSplitting.cpp | 80 for (const Inst &Instr : Node->getInsts()) { in reset() local
81 if (Instr.isDeleted()) in reset()
83 for (SizeT i = 0; i < Instr.getSrcSize(); ++i) { in reset()
84 if (auto *SrcVar = llvm::dyn_cast<Variable>(Instr.getSrc(i))) { in reset()
86 Map[VarNum].LastUseInst = &Instr; in reset()
141 bool isInstLastUseOfVar(const Variable *Var, const Inst *Instr) { in isInstLastUseOfVar() argument
142 return Map[getVarNum(Var)].LastUseInst == Instr; in isInstLastUseOfVar()
190 Instr = CurInst; in setInst()
191 Dest = Instr->getDest(); in setInst()
221 Instr->getNumber())) { in handleUnwantedInstruction()
[all …]
|
| D | IceTargetLowering.cpp | 82 void LoweringContext::insert(Inst *Instr) { in insert() argument
83 getNode()->getInsts().insert(Next, Instr); in insert()
84 LastInserted = Instr; in insert()
111 Inst *Instr = LastInserted; in availabilityUpdate() local
112 if (Instr == nullptr) in availabilityUpdate()
114 if (!Instr->isVarAssign()) in availabilityUpdate()
117 LastDest = Instr->getDest(); in availabilityUpdate()
118 LastSrc = llvm::cast<Variable>(Instr->getSrc(0)); in availabilityUpdate()
391 Inst *Instr = iteratorToInst(Context.getCur()); in lower() local
392 Instr->deleteIfDead(); in lower()
[all …]
|
| D | IceTargetLowering.h | 53 #define UnimplementedLoweringError(Target, Instr) \ argument
56 (Target)->addFakeDefUses(Instr); \
61 (std::string("Not yet implemented: ") + Instr->getInstName()) \
96 void insert(Inst *Instr);
222 void lowerInst(CfgNode *Node, InstList::iterator Next, InstHighLevel *Instr);
393 virtual void lowerAlloca(const InstAlloca *Instr) = 0;
394 virtual void lowerArithmetic(const InstArithmetic *Instr) = 0;
395 virtual void lowerAssign(const InstAssign *Instr) = 0;
396 virtual void lowerBr(const InstBr *Instr) = 0;
397 virtual void lowerBreakpoint(const InstBreakpoint *Instr) = 0;
[all …]
|
| D | IceInst.h | 305 static bool classof(const Inst *Instr) { return Instr->getKind() == Alloca; } in classof() argument
343 static bool classof(const Inst *Instr) { in classof() argument
344 return Instr->getKind() == Arithmetic; in classof()
371 static bool classof(const Inst *Instr) { return Instr->getKind() == Assign; } in classof() argument
412 static bool classof(const Inst *Instr) { return Instr->getKind() == Br; } in classof() argument
453 static bool classof(const Inst *Instr) { return Instr->getKind() == Call; } in classof() argument
496 static bool classof(const Inst *Instr) { return Instr->getKind() == Cast; } in classof() argument
519 static bool classof(const Inst *Instr) { in classof() argument
520 return Instr->getKind() == ExtractElement; in classof()
551 static bool classof(const Inst *Instr) { return Instr->getKind() == Fcmp; } in classof() argument
[all …]
|
| D | IceCfg.cpp | 231 for (auto &Instr : Node->getPhis()) { in fixPhiNodes() local
232 auto *Phi = llvm::cast<InstPhi>(&Instr); in fixPhiNodes()
463 size_t operator()(const Inst *Instr) const { in localCSE()
464 auto Kind = Instr->getKind(); in localCSE()
468 for (SizeT i = 0; i < Instr->getSrcSize(); ++i) { in localCSE()
469 Result ^= Instr->getSrc(i)->hashValue(); in localCSE()
521 for (Inst &Instr : Node->getInsts()) { in localCSE()
522 if (Instr.isDeleted() || !llvm::isa<InstArithmetic>(&Instr)) in localCSE()
526 auto Iter = Replacements.find(Instr.getDest()); in localCSE()
532 auto DepIter = Dependency.find(Instr.getDest()); in localCSE()
[all …]
|
| D | IceTargetLoweringARM32.cpp | 446 void TargetARM32::genTargetHelperCallFor(Inst *Instr) { in genTargetHelperCallFor() argument
450 switch (Instr->getKind()) { in genTargetHelperCallFor()
454 Variable *Dest = Instr->getDest(); in genTargetHelperCallFor()
457 llvm::cast<InstArithmetic>(Instr)->getOp(); in genTargetHelperCallFor()
468 scalarizeArithmetic(Op, Dest, Instr->getSrc(0), Instr->getSrc(1)); in genTargetHelperCallFor()
469 Instr->setDeleted(); in genTargetHelperCallFor()
502 Call->addArg(Instr->getSrc(0)); in genTargetHelperCallFor()
503 Call->addArg(Instr->getSrc(1)); in genTargetHelperCallFor()
504 Instr->setDeleted(); in genTargetHelperCallFor()
540 Operand *Src0 = Instr->getSrc(0); in genTargetHelperCallFor()
[all …]
|
| /external/llvm-project/llvm/tools/llvm-cfi-verify/lib/ |
| D | FileAnalysis.h | 78 struct Instr { struct
98 const Instr *getInstruction(uint64_t Address) const;
102 const Instr &getInstructionOrDie(uint64_t Address) const;
107 const Instr *getPrevInstructionSequential(const Instr &InstrMeta) const;
108 const Instr *getNextInstructionSequential(const Instr &InstrMeta) const;
111 bool isCFITrap(const Instr &InstrMeta) const;
115 bool willTrapOnCFIViolation(const Instr &InstrMeta) const;
121 bool canFallThrough(const Instr &InstrMeta) const;
130 const Instr *getDefiniteNextInstruction(const Instr &InstrMeta) const;
135 std::set<const Instr *>
[all …]
|
| D | FileAnalysis.cpp | 39 using Instr = llvm::cfi_verify::FileAnalysis::Instr; typedef
121 const Instr *
122 FileAnalysis::getPrevInstructionSequential(const Instr &InstrMeta) const { in getPrevInstructionSequential()
123 std::map<uint64_t, Instr>::const_iterator KV = in getPrevInstructionSequential()
134 const Instr *
135 FileAnalysis::getNextInstructionSequential(const Instr &InstrMeta) const { in getNextInstructionSequential()
136 std::map<uint64_t, Instr>::const_iterator KV = in getNextInstructionSequential()
147 bool FileAnalysis::usesRegisterOperand(const Instr &InstrMeta) const { in usesRegisterOperand()
155 const Instr *FileAnalysis::getInstruction(uint64_t Address) const { in getInstruction()
163 const Instr &FileAnalysis::getInstructionOrDie(uint64_t Address) const { in getInstructionOrDie()
[all …]
|
| /external/llvm-project/llvm/tools/llvm-exegesis/lib/ |
| D | CodeTemplate.cpp | 18 InstructionTemplate::InstructionTemplate(const Instruction *Instr) in InstructionTemplate() argument
19 : Instr(Instr), VariableValues(Instr->Variables.size()) {} in InstructionTemplate()
32 return Instr->Description.getOpcode(); in getOpcode()
44 return getValueFor(Instr->Variables[Op.getVariableIndex()]); in getValueFor()
48 return getValueFor(Instr->Variables[Op.getVariableIndex()]); in getValueFor()
52 return any_of(Instr->Variables, [this](const Variable &Var) { in hasImmediateVariables()
53 return Instr->getPrimaryOperand(Var).isImmediate(); in hasImmediateVariables()
59 Result.setOpcode(Instr->Description.Opcode); in build()
60 for (const auto &Op : Instr->Operands) in build()
|
| D | SerialSnippetGenerator.cpp | 38 computeAliasingInstructions(const LLVMState &State, const Instruction *Instr, in computeAliasingInstructions() argument
49 if (OtherOpcode == Instr->Description.getOpcode()) in computeAliasingInstructions()
63 if (Instr->hasAliasingRegistersThrough(OtherInstr, ForbiddenRegisters)) in computeAliasingInstructions()
71 static ExecutionMode getExecutionModes(const Instruction &Instr, in getExecutionModes() argument
74 if (Instr.hasAliasingImplicitRegisters()) in getExecutionModes()
76 if (Instr.hasTiedRegisters()) in getExecutionModes()
78 if (Instr.hasMemoryOperands()) in getExecutionModes()
81 if (Instr.hasAliasingRegisters(ForbiddenRegisters)) in getExecutionModes()
83 if (Instr.hasOneUseOrOneDef()) in getExecutionModes()
133 const Instruction &Instr = Variant.getInstr(); in appendCodeTemplates() local
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMFeatures.h | 21 bool IsCPSRDead(const InstrType *Instr);
24 inline bool isV8EligibleForIT(const InstrType *Instr) { in isV8EligibleForIT() argument
25 switch (Instr->getOpcode()) { in isV8EligibleForIT()
52 return IsCPSRDead(Instr); in isV8EligibleForIT()
78 return Instr->getOperand(2).getReg() != ARM::PC; in isV8EligibleForIT()
83 return Instr->getOperand(0).getReg() != ARM::PC; in isV8EligibleForIT()
85 return Instr->getOperand(0).getReg() != ARM::PC && in isV8EligibleForIT()
86 Instr->getOperand(2).getReg() != ARM::PC; in isV8EligibleForIT()
89 return Instr->getOperand(0).getReg() != ARM::PC && in isV8EligibleForIT()
90 Instr->getOperand(1).getReg() != ARM::PC; in isV8EligibleForIT()
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMFeatures.h | 21 bool IsCPSRDead(const InstrType *Instr);
24 inline bool isV8EligibleForIT(const InstrType *Instr) { in isV8EligibleForIT() argument
25 switch (Instr->getOpcode()) { in isV8EligibleForIT()
52 return IsCPSRDead(Instr); in isV8EligibleForIT()
78 return Instr->getOperand(2).getReg() != ARM::PC; in isV8EligibleForIT()
83 return Instr->getOperand(0).getReg() != ARM::PC; in isV8EligibleForIT()
85 return Instr->getOperand(0).getReg() != ARM::PC && in isV8EligibleForIT()
86 Instr->getOperand(2).getReg() != ARM::PC; in isV8EligibleForIT()
89 return Instr->getOperand(0).getReg() != ARM::PC && in isV8EligibleForIT()
90 Instr->getOperand(1).getReg() != ARM::PC; in isV8EligibleForIT()
|
| D | MVEVPTOptimisationsPass.cpp | 65 MachineInstr &Instr,
309 static ARMCC::CondCodes GetCondCode(MachineInstr &Instr) { in GetCondCode() argument
310 assert(IsVCMP(Instr.getOpcode()) && "Inst must be a VCMP"); in GetCondCode()
311 return ARMCC::CondCodes(Instr.getOperand(3).getImm()); in GetCondCode()
342 static bool IsWritingToVCCR(MachineInstr &Instr) { in IsWritingToVCCR() argument
343 if (Instr.getNumOperands() == 0) in IsWritingToVCCR()
345 MachineOperand &Dst = Instr.getOperand(0); in IsWritingToVCCR()
351 MachineRegisterInfo &RegInfo = Instr.getMF()->getRegInfo(); in IsWritingToVCCR()
365 MachineBasicBlock &MBB, MachineInstr &Instr, MachineOperand &User, in ReplaceRegisterUseWithVPNOT() argument
370 BuildMI(MBB, &Instr, Instr.getDebugLoc(), TII->get(ARM::MVE_VPNOT)) in ReplaceRegisterUseWithVPNOT()
[all …]
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMFeatures.h | 22 bool IsCPSRDead(InstrType *Instr);
25 inline bool isV8EligibleForIT(InstrType *Instr) { in isV8EligibleForIT() argument
26 switch (Instr->getOpcode()) { in isV8EligibleForIT()
53 return IsCPSRDead(Instr); in isV8EligibleForIT()
79 return Instr->getOperand(2).getReg() != ARM::PC; in isV8EligibleForIT()
84 return Instr->getOperand(0).getReg() != ARM::PC; in isV8EligibleForIT()
86 return Instr->getOperand(0).getReg() != ARM::PC && in isV8EligibleForIT()
87 Instr->getOperand(2).getReg() != ARM::PC; in isV8EligibleForIT()
90 return Instr->getOperand(0).getReg() != ARM::PC && in isV8EligibleForIT()
91 Instr->getOperand(1).getReg() != ARM::PC; in isV8EligibleForIT()
|
| /external/llvm-project/llvm/tools/llvm-exegesis/lib/X86/ |
| D | Target.cpp | 57 static const char *isInvalidMemoryInstr(const Instruction &Instr) { in isInvalidMemoryInstr() argument
58 switch (Instr.Description.TSFlags & X86II::FormMask) { in isInvalidMemoryInstr()
157 return (Instr.Description.Opcode == X86::POP16r || in isInvalidMemoryInstr()
158 Instr.Description.Opcode == X86::POP32r || in isInvalidMemoryInstr()
159 Instr.Description.Opcode == X86::PUSH16r || in isInvalidMemoryInstr()
160 Instr.Description.Opcode == X86::PUSH32r) in isInvalidMemoryInstr()
192 static const char *isInvalidOpcode(const Instruction &Instr) { in isInvalidOpcode() argument
193 const auto OpcodeName = Instr.Name; in isInvalidOpcode()
194 if ((Instr.Description.TSFlags & X86II::FormMask) == X86II::Pseudo) in isInvalidOpcode()
199 if (const auto reason = isInvalidMemoryInstr(Instr)) in isInvalidOpcode()
[all …]
|
| /external/llvm-project/llvm/lib/Transforms/Scalar/ |
| D | CorrelatedValuePropagation.cpp | 620 static bool narrowSDivOrSRem(BinaryOperator *Instr, LazyValueInfo *LVI) { in narrowSDivOrSRem() argument
621 assert(Instr->getOpcode() == Instruction::SDiv || in narrowSDivOrSRem()
622 Instr->getOpcode() == Instruction::SRem); in narrowSDivOrSRem()
623 if (Instr->getType()->isVectorTy()) in narrowSDivOrSRem()
628 unsigned OrigWidth = Instr->getType()->getIntegerBitWidth(); in narrowSDivOrSRem()
634 for (auto I : zip(Instr->operands(), CRs)) { in narrowSDivOrSRem()
635 std::get<1>(I) = LVI->getConstantRange(std::get<0>(I), Instr); in narrowSDivOrSRem()
655 IRBuilder<> B{Instr}; in narrowSDivOrSRem()
656 auto *TruncTy = Type::getIntNTy(Instr->getContext(), NewWidth); in narrowSDivOrSRem()
657 auto *LHS = B.CreateTruncOrBitCast(Instr->getOperand(0), TruncTy, in narrowSDivOrSRem()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Analysis/ |
| D | VectorUtils.h | 423 InterleaveGroup(InstTy *Instr, int32_t Stride, Align Alignment) in InterleaveGroup() argument
424 : Alignment(Alignment), InsertPos(Instr) { in InterleaveGroup()
429 Members[0] = Instr; in InterleaveGroup()
442 bool insertMember(InstTy *Instr, int32_t Index, Align NewAlign) { in insertMember() argument
475 Members[Key] = Instr; in insertMember()
493 uint32_t getIndex(const InstTy *Instr) const { in getIndex() argument
495 if (I.second == Instr) in getIndex()
589 bool isInterleaved(Instruction *Instr) const { in isInterleaved() argument
590 return InterleaveGroupMap.find(Instr) != InterleaveGroupMap.end(); in isInterleaved()
597 getInterleaveGroup(const Instruction *Instr) const { in getInterleaveGroup() argument
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600OptimizeVectorRegisters.cpp | 71 MachineInstr *Instr; member in __anonc51491020111::RegSeqInfo
75 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) { in RegSeqInfo()
77 for (unsigned i = 1, e = Instr->getNumOperands(); i < e; i+=2) { in RegSeqInfo()
78 MachineOperand &MO = Instr->getOperand(i); in RegSeqInfo()
79 unsigned Chan = Instr->getOperand(i + 1).getImm(); in RegSeqInfo()
90 return RSI.Instr == Instr; in operator ==()
200 Register Reg = RSI->Instr->getOperand(0).getReg(); in RebuildVector()
201 MachineBasicBlock::iterator Pos = RSI->Instr; in RebuildVector()
205 Register SrcVec = BaseRSI->Instr->getOperand(0).getReg(); in RebuildVector()
241 RSI->Instr->eraseFromParent(); in RebuildVector()
[all …]
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | R600OptimizeVectorRegisters.cpp | 65 MachineInstr *Instr; member in __anon1127cfe00111::RegSeqInfo
68 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) { in RegSeqInfo()
70 for (unsigned i = 1, e = Instr->getNumOperands(); i < e; i+=2) { in RegSeqInfo()
71 MachineOperand &MO = Instr->getOperand(i); in RegSeqInfo()
72 unsigned Chan = Instr->getOperand(i + 1).getImm(); in RegSeqInfo()
82 return RSI.Instr == Instr; in operator ==()
182 unsigned Reg = RSI->Instr->getOperand(0).getReg(); in RebuildVector()
183 MachineBasicBlock::iterator Pos = RSI->Instr; in RebuildVector()
187 unsigned SrcVec = BaseRSI->Instr->getOperand(0).getReg(); in RebuildVector()
225 RSI->Instr->eraseFromParent(); in RebuildVector()
[all …]
|
| /external/llvm-project/llvm/utils/TableGen/GlobalISel/ |
| D | GIMatchDagPredicate.cpp | 27 GIMatchDagContext &Ctx, StringRef Name, const CodeGenInstruction &Instr) in GIMatchDagOpcodePredicate() argument
30 Instr(Instr) {} in GIMatchDagOpcodePredicate()
33 OS << "$mi.getOpcode() == " << Instr.TheDef->getName(); in printDescription()
44 for (const CodeGenInstruction *Instr : Instrs) { in printDescription() local
45 OS << Separator << Instr->TheDef->getName(); in printDescription()
|
| /external/llvm-project/llvm/lib/Target/Lanai/Disassembler/ |
| D | LanaiDisassembler.cpp | 90 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) { in PostOperandDecodeAdjust() argument
94 if (isRMOpcode(Instr.getOpcode())) in PostOperandDecodeAdjust()
96 else if (isSPLSOpcode(Instr.getOpcode())) in PostOperandDecodeAdjust()
98 else if (isRRMOpcode(Instr.getOpcode())) { in PostOperandDecodeAdjust()
112 if (Instr.getOperand(2).isReg()) { in PostOperandDecodeAdjust()
113 Instr.getOperand(2).setReg(Lanai::R0); in PostOperandDecodeAdjust()
115 if (Instr.getOperand(2).isImm()) in PostOperandDecodeAdjust()
116 Instr.getOperand(2).setImm(0); in PostOperandDecodeAdjust()
127 Instr.addOperand(MCOperand::createImm(AluOp)); in PostOperandDecodeAdjust()
132 LanaiDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, in getInstruction() argument
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/Disassembler/ |
| D | LanaiDisassembler.cpp | 90 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) { in PostOperandDecodeAdjust() argument
94 if (isRMOpcode(Instr.getOpcode())) in PostOperandDecodeAdjust()
96 else if (isSPLSOpcode(Instr.getOpcode())) in PostOperandDecodeAdjust()
98 else if (isRRMOpcode(Instr.getOpcode())) { in PostOperandDecodeAdjust()
112 if (Instr.getOperand(2).isReg()) { in PostOperandDecodeAdjust()
113 Instr.getOperand(2).setReg(Lanai::R0); in PostOperandDecodeAdjust()
115 if (Instr.getOperand(2).isImm()) in PostOperandDecodeAdjust()
116 Instr.getOperand(2).setImm(0); in PostOperandDecodeAdjust()
127 Instr.addOperand(MCOperand::createImm(AluOp)); in PostOperandDecodeAdjust()
132 LanaiDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, in getInstruction() argument
[all …]
|
| /external/llvm/lib/Target/Lanai/Disassembler/ |
| D | LanaiDisassembler.cpp | 89 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) { in PostOperandDecodeAdjust() argument
93 if (isRMOpcode(Instr.getOpcode())) in PostOperandDecodeAdjust()
95 else if (isSPLSOpcode(Instr.getOpcode())) in PostOperandDecodeAdjust()
97 else if (isRRMOpcode(Instr.getOpcode())) { in PostOperandDecodeAdjust()
111 if (Instr.getOperand(2).isReg()) { in PostOperandDecodeAdjust()
112 Instr.getOperand(2).setReg(Lanai::R0); in PostOperandDecodeAdjust()
114 if (Instr.getOperand(2).isImm()) in PostOperandDecodeAdjust()
115 Instr.getOperand(2).setImm(0); in PostOperandDecodeAdjust()
126 Instr.addOperand(MCOperand::createImm(AluOp)); in PostOperandDecodeAdjust()
130 DecodeStatus LanaiDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, in getInstruction() argument
[all …]
|