| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 1173 for (unsigned IntReg = LargestIntReg - 1; in computeRegisterProperties() local
1174 IntReg >= (unsigned)MVT::i1; --IntReg) { in computeRegisterProperties()
1175 MVT IVT = (MVT::SimpleValueType)IntReg; in computeRegisterProperties()
1177 LegalIntReg = IntReg; in computeRegisterProperties()
1179 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = in computeRegisterProperties()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 1322 for (unsigned IntReg = LargestIntReg - 1; in computeRegisterProperties() local
1323 IntReg >= (unsigned)MVT::i1; --IntReg) { in computeRegisterProperties()
1324 MVT IVT = (MVT::SimpleValueType)IntReg; in computeRegisterProperties()
1326 LegalIntReg = IntReg; in computeRegisterProperties()
1328 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = in computeRegisterProperties()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 1319 for (unsigned IntReg = LargestIntReg - 1; in computeRegisterProperties() local
1320 IntReg >= (unsigned)MVT::i1; --IntReg) { in computeRegisterProperties()
1321 MVT IVT = (MVT::SimpleValueType)IntReg; in computeRegisterProperties()
1323 LegalIntReg = IntReg; in computeRegisterProperties()
1325 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = in computeRegisterProperties()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 1162 unsigned IntReg = PPCMoveToIntReg(I, DstVT, DestReg, IsSigned); in SelectFPToI() local
1163 if (IntReg == 0) in SelectFPToI()
1166 updateValueMap(I, IntReg); in SelectFPToI()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 1500 unsigned IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), in selectFNeg() local
1502 if (!IntReg) in selectFNeg()
1506 IntVT.getSimpleVT(), ISD::XOR, IntReg, /*IsKill=*/true, in selectFNeg()
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 1259 unsigned IntReg = Subtarget->hasSPE() in SelectFPToI() local
1263 if (IntReg == 0) in SelectFPToI()
1266 updateValueMap(I, IntReg); in SelectFPToI()
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 1800 Register IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), in selectFNeg() local
1802 if (!IntReg) in selectFNeg()
1806 IntVT.getSimpleVT(), ISD::XOR, IntReg, /*Op0IsKill=*/true, in selectFNeg()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 1257 unsigned IntReg = PPCSubTarget->hasSPE() ? DestReg : in SelectFPToI() local
1260 if (IntReg == 0) in SelectFPToI()
1263 updateValueMap(I, IntReg); in SelectFPToI()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 1733 unsigned IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), in selectFNeg() local
1735 if (!IntReg) in selectFNeg()
1739 IntVT.getSimpleVT(), ISD::XOR, IntReg, /*IsKill=*/true, in selectFNeg()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 1608 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg); in SelectFPToI() local
1609 if (IntReg == 0) return false; in SelectFPToI()
1611 updateValueMap(I, IntReg); in SelectFPToI()
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 1595 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg); in SelectFPToI() local
1596 if (IntReg == 0) return false; in SelectFPToI()
1598 updateValueMap(I, IntReg); in SelectFPToI()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 1603 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg); in SelectFPToI() local
1604 if (IntReg == 0) return false; in SelectFPToI()
1606 updateValueMap(I, IntReg); in SelectFPToI()
|