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Searched refs:IsDef (Results 1 – 25 of 68) sorted by relevance

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/external/llvm-project/llvm/utils/TableGen/GlobalISel/
DGIMatchDagOperands.h48 bool IsDef; variable
51 GIMatchDagOperand(unsigned Idx, StringRef Name, bool IsDef) in GIMatchDagOperand() argument
52 : Idx(Idx), Name(Name), IsDef(IsDef) {} in GIMatchDagOperand()
56 bool isDef() const { return IsDef; } in isDef()
66 bool IsDef);
95 void add(StringRef Name, unsigned Idx, bool IsDef);
DGIMatchDagOperands.cpp16 Profile(ID, Idx, Name, IsDef); in Profile()
20 StringRef Name, bool IsDef) { in Profile() argument
23 ID.AddBoolean(IsDef); in Profile()
26 void GIMatchDagOperandList::add(StringRef Name, unsigned Idx, bool IsDef) { in add() argument
28 Operands.emplace_back(Operands.size(), Name, IsDef); in add()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DMachineOperand.h95 unsigned IsDef : 1; variable
370 return !IsDef; in isUse()
375 return IsDef; in isDef()
385 return IsDeadOrKill & IsDef; in isDead()
390 return IsDeadOrKill & !IsDef; in isKill()
499 assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
505 assert(isReg() && IsDef && "Wrong MachineOperand mutator");
522 assert(isReg() && IsDef && "Wrong MachineOperand mutator");
527 assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
789 Op.IsDef = isDef;
/external/llvm/include/llvm/CodeGen/
DMachineOperand.h87 bool IsDef : 1; variable
279 return !IsDef; in isUse()
284 return IsDef; in isDef()
376 assert(isReg() && !IsDef && "Wrong MachineOperand accessor");
382 assert(isReg() && IsDef && "Wrong MachineOperand accessor");
397 assert(isReg() && IsDef && "Wrong MachineOperand accessor");
402 assert(isReg() && !IsDef && "Wrong MachineOperand accessor");
616 Op.IsDef = isDef;
/external/llvm-project/llvm/include/llvm/CodeGen/
DMachineOperand.h95 unsigned IsDef : 1; variable
370 return !IsDef; in isUse()
375 return IsDef; in isDef()
385 return IsDeadOrKill & IsDef; in isDead()
390 return IsDeadOrKill & !IsDef; in isKill()
499 assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
505 assert(isReg() && IsDef && "Wrong MachineOperand mutator");
522 assert(isReg() && IsDef && "Wrong MachineOperand mutator");
527 assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
799 Op.IsDef = isDef;
/external/llvm-project/llvm/utils/TableGen/
DInstrDocsEmitter.cpp156 bool IsDef = i < II->Operands.NumDefs; in EmitInstrDocs() local
170 OS << "* " << (IsDef ? "DEF" : "USE") << " ``" << Op.Rec->getName() in EmitInstrDocs()
181 OS << "* " << (IsDef ? "DEF" : "USE") << " ``" << Op.Rec->getName() in EmitInstrDocs()
/external/llvm-project/llvm/tools/llvm-exegesis/lib/
DMCInstrDescView.cpp44 bool Operand::isDef() const { return IsDef; } in isDef()
46 bool Operand::isUse() const { return !IsDef; } in isUse()
117 Operand.IsDef = (OpIndex < Description->getNumDefs()); in create()
135 Operand.IsDef = true; in create()
144 Operand.IsDef = false; in create()
DMCInstrDescView.h86 bool IsDef = false; member
DAssembler.cpp101 const bool IsDef = OpIndex < MCID.getNumDefs(); in addInstruction() local
104 if (IsDef && !OpInfo.isOptionalDef()) in addInstruction()
/external/llvm/lib/Target/Hexagon/
DRDFDeadCode.cpp125 if (DFG.IsDef(RA)) in collect()
140 for (NodeAddr<DefNode*> DA : IA.Addr->members_if(DFG.IsDef, DFG)) in collect()
215 else if (DFG.IsDef(RA)) in erase()
DHexagonRDFOpt.cpp152 if (DFG.IsDef(RA) && DeadNodes.count(RA.Id)) in run()
244 for (NodeAddr<DefNode*> DA : IA.Addr->members_if(DFG.IsDef, DFG)) { in rewrite()
/external/llvm-project/llvm/lib/Target/Hexagon/
DRDFDeadCode.cpp136 if (DFG.IsDef(RA)) in collect()
151 for (NodeAddr<DefNode*> DA : IA.Addr->members_if(DFG.IsDef, DFG)) in collect()
226 else if (DFG.IsDef(RA)) in erase()
DHexagonConstExtenders.cpp327 bool IsDef = false; member
502 if (ED.IsDef) in operator <<()
1163 ED.IsDef = true; in recordExtender()
1183 ED.IsDef = true; in recordExtender()
1188 ED.IsDef = true; in recordExtender()
1192 ED.IsDef = true; in recordExtender()
1274 if (!ED.IsDef) in assignInits()
1294 if (ED.IsDef) in assignInits()
1850 assert((!ED.IsDef || ED.Rd.Reg != 0) && "Missing Rd for def"); in replaceInstr()
1875 if (ED.IsDef && Diff != 0) { in replaceInstr()
[all …]
DHexagonRDFOpt.cpp168 if (DFG.IsDef(RA) && DeadNodes.count(RA.Id)) in run()
258 for (NodeAddr<DefNode*> DA : IA.Addr->members_if(DFG.IsDef, DFG)) { in rewrite()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DRDFDeadCode.cpp136 if (DFG.IsDef(RA)) in collect()
151 for (NodeAddr<DefNode*> DA : IA.Addr->members_if(DFG.IsDef, DFG)) in collect()
226 else if (DFG.IsDef(RA)) in erase()
DHexagonConstExtenders.cpp329 bool IsDef = false; member
503 if (ED.IsDef) in operator <<()
1164 ED.IsDef = true; in recordExtender()
1184 ED.IsDef = true; in recordExtender()
1189 ED.IsDef = true; in recordExtender()
1193 ED.IsDef = true; in recordExtender()
1275 if (!ED.IsDef) in assignInits()
1295 if (ED.IsDef) in assignInits()
1833 assert((!ED.IsDef || ED.Rd.Reg != 0) && "Missing Rd for def"); in replaceInstr()
1858 if (ED.IsDef && Diff != 0) { in replaceInstr()
[all …]
DHexagonRDFOpt.cpp168 if (DFG.IsDef(RA) && DeadNodes.count(RA.Id)) in run()
258 for (NodeAddr<DefNode*> DA : IA.Addr->members_if(DFG.IsDef, DFG)) { in rewrite()
/external/llvm/test/CodeGen/PowerPC/
Dsplit-index-tc.ll23 …%IsDef.i = getelementptr inbounds %"class.llvm::MachineOperand", %"class.llvm::MachineOperand"* %0…
24 %1 = bitcast [3 x i8]* %IsDef.i to i24*
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dsplit-index-tc.ll23 …%IsDef.i = getelementptr inbounds %"class.llvm::MachineOperand", %"class.llvm::MachineOperand"* %0…
24 %1 = bitcast [3 x i8]* %IsDef.i to i24*
/external/llvm/lib/CodeGen/
DMIRPrinter.cpp124 const MachineRegisterInfo *MRI = nullptr, bool IsDef = false);
752 const MachineRegisterInfo *MRI, bool IsDef) { in print() argument
758 else if (!IsDef && Op.isDef()) in print()
779 assert((!IsDef || MRI) && "for IsDef, MRI must be provided"); in print()
780 if (IsDef && MRI->getSize(Op.getReg())) in print()
/external/llvm/lib/Target/Mips/
DMipsSEISelDAGToDAG.h31 void addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
DMipsDelaySlotFiller.cpp112 bool IsDef) const;
404 unsigned Reg, bool IsDef) const { in checkRegDefsUses()
405 if (IsDef) { in checkRegDefsUses()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsSEISelDAGToDAG.h32 void addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
/external/llvm-project/llvm/lib/Target/Mips/
DMipsSEISelDAGToDAG.h32 void addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
DMipsDelaySlotFiller.cpp130 bool IsDef) const;
435 unsigned Reg, bool IsDef) const { in checkRegDefsUses()
436 if (IsDef) { in checkRegDefsUses()

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