| /external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | Utils.h | 259 bool IsFP);
263 int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP);
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| D | MachineIRBuilder.h | 647 unsigned getBoolExtOp(bool IsVec, bool IsFP) const;
652 bool IsFP);
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| /external/llvm-project/clang/include/clang/Basic/ |
| D | AArch64SVEACLETypes.def | 15 // SVE_VECTOR_TYPE(Name, Id, SingletonId, ElKind, ElBits, IsSigned, IsFP) -
36 // - IsFP is true for vectors of floating-point elements.
43 IsSigned, IsFP, IsBF) \
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 5646 bool IsFP = ValueSVT.isFloatingPoint(); in Select() local
5653 Opc = IsFP ? X86::VGATHERDPSZ128rm : X86::VPGATHERDDZ128rm; in Select()
5655 Opc = IsFP ? X86::VGATHERDPSZ256rm : X86::VPGATHERDDZ256rm; in Select()
5657 Opc = IsFP ? X86::VGATHERDPSZrm : X86::VPGATHERDDZrm; in Select()
5659 Opc = IsFP ? X86::VGATHERDPDZ128rm : X86::VPGATHERDQZ128rm; in Select()
5661 Opc = IsFP ? X86::VGATHERDPDZ256rm : X86::VPGATHERDQZ256rm; in Select()
5663 Opc = IsFP ? X86::VGATHERDPDZrm : X86::VPGATHERDQZrm; in Select()
5665 Opc = IsFP ? X86::VGATHERQPSZ128rm : X86::VPGATHERQDZ128rm; in Select()
5667 Opc = IsFP ? X86::VGATHERQPSZ256rm : X86::VPGATHERQDZ256rm; in Select()
5669 Opc = IsFP ? X86::VGATHERQPSZrm : X86::VPGATHERQDZrm; in Select()
[all …]
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| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | Utils.cpp | 725 bool IsFP) { in isConstTrueVal() argument
726 switch (TLI.getBooleanContents(IsVector, IsFP)) { in isConstTrueVal()
738 bool IsFP) { in getICmpTrueVal() argument
739 switch (TLI.getBooleanContents(IsVector, IsFP)) { in getICmpTrueVal()
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| D | MachineIRBuilder.cpp | 419 unsigned MachineIRBuilder::getBoolExtOp(bool IsVec, bool IsFP) const { in getBoolExtOp()
421 switch (TLI->getBooleanContents(IsVec, IsFP)) { in getBoolExtOp()
433 bool IsFP) { in buildBoolExt() argument
434 unsigned ExtOp = getBoolExtOp(getMRI()->getType(Op.getReg()).isVector(), IsFP); in buildBoolExt()
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| D | CombinerHelper.cpp | 2944 int64_t Cst, bool IsVector, bool IsFP) { in isConstValidTrue() argument
2947 isConstTrueVal(TLI, Cst, IsVector, IsFP); in isConstValidTrue()
2971 bool IsFP = false; in matchNotCmp() local
2983 if (IsFP) in matchNotCmp()
2991 IsFP = true; in matchNotCmp()
3015 if (!isConstValidTrue(TLI, Ty.getScalarSizeInBits(), *MaybeCst, true, IsFP)) in matchNotCmp()
3020 if (!isConstValidTrue(TLI, Ty.getSizeInBits(), Cst, false, IsFP)) in matchNotCmp()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.h | 101 bool IsFP) const;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.h | 112 bool IsFP) const;
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.h | 112 bool IsFP) const;
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 834 NodeType getExtForLoadExtType(bool IsFP, LoadExtType);
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Bitcode/Reader/ |
| D | BitcodeReader.cpp | 1059 bool IsFP = Ty->isFPOrFPVectorTy(); in getDecodedUnaryOpcode() local
1061 if (!IsFP && !Ty->isIntOrIntVectorTy()) in getDecodedUnaryOpcode()
1068 return IsFP ? Instruction::FNeg : -1; in getDecodedUnaryOpcode()
1073 bool IsFP = Ty->isFPOrFPVectorTy(); in getDecodedBinaryOpcode() local
1075 if (!IsFP && !Ty->isIntOrIntVectorTy()) in getDecodedBinaryOpcode()
1082 return IsFP ? Instruction::FAdd : Instruction::Add; in getDecodedBinaryOpcode()
1084 return IsFP ? Instruction::FSub : Instruction::Sub; in getDecodedBinaryOpcode()
1086 return IsFP ? Instruction::FMul : Instruction::Mul; in getDecodedBinaryOpcode()
1088 return IsFP ? -1 : Instruction::UDiv; in getDecodedBinaryOpcode()
1090 return IsFP ? Instruction::FDiv : Instruction::SDiv; in getDecodedBinaryOpcode()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 1031 NodeType getExtForLoadExtType(bool IsFP, LoadExtType);
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIFrameLowering.cpp | 74 bool IsFP) { in getVGPRSpillLaneOrTempRegister() argument
97 dbgs() << "Spilling " << (IsFP ? "FP" : "BP") << " to " in getVGPRSpillLaneOrTempRegister()
118 dbgs() << (IsFP ? "FP" : "BP") << " requires fallback spill to " in getVGPRSpillLaneOrTempRegister()
126 << (IsFP ? "FP" : "BP") << '\n'); in getVGPRSpillLaneOrTempRegister()
129 LLVM_DEBUG(dbgs() << "Saving " << (IsFP ? "FP" : "BP") << " with copy to " in getVGPRSpillLaneOrTempRegister()
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 1247 NodeType getExtForLoadExtType(bool IsFP, LoadExtType);
|
| /external/llvm-project/llvm/lib/Bitcode/Reader/ |
| D | BitcodeReader.cpp | 1065 bool IsFP = Ty->isFPOrFPVectorTy(); in getDecodedUnaryOpcode() local
1067 if (!IsFP && !Ty->isIntOrIntVectorTy()) in getDecodedUnaryOpcode()
1074 return IsFP ? Instruction::FNeg : -1; in getDecodedUnaryOpcode()
1079 bool IsFP = Ty->isFPOrFPVectorTy(); in getDecodedBinaryOpcode() local
1081 if (!IsFP && !Ty->isIntOrIntVectorTy()) in getDecodedBinaryOpcode()
1088 return IsFP ? Instruction::FAdd : Instruction::Add; in getDecodedBinaryOpcode()
1090 return IsFP ? Instruction::FSub : Instruction::Sub; in getDecodedBinaryOpcode()
1092 return IsFP ? Instruction::FMul : Instruction::Mul; in getDecodedBinaryOpcode()
1094 return IsFP ? -1 : Instruction::UDiv; in getDecodedBinaryOpcode()
1096 return IsFP ? Instruction::FDiv : Instruction::SDiv; in getDecodedBinaryOpcode()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.cpp | 424 unsigned MachineIRBuilder::getBoolExtOp(bool IsVec, bool IsFP) const { in getBoolExtOp()
426 switch (TLI->getBooleanContents(IsVec, IsFP)) { in getBoolExtOp()
438 bool IsFP) { in buildBoolExt() argument
439 unsigned ExtOp = getBoolExtOp(getMRI()->getType(Op.getReg()).isVector(), IsFP); in buildBoolExt()
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| /external/llvm/lib/Bitcode/Reader/ |
| D | BitcodeReader.cpp | 794 bool IsFP = Ty->isFPOrFPVectorTy(); in getDecodedBinaryOpcode() local
796 if (!IsFP && !Ty->isIntOrIntVectorTy()) in getDecodedBinaryOpcode()
803 return IsFP ? Instruction::FAdd : Instruction::Add; in getDecodedBinaryOpcode()
805 return IsFP ? Instruction::FSub : Instruction::Sub; in getDecodedBinaryOpcode()
807 return IsFP ? Instruction::FMul : Instruction::Mul; in getDecodedBinaryOpcode()
809 return IsFP ? -1 : Instruction::UDiv; in getDecodedBinaryOpcode()
811 return IsFP ? Instruction::FDiv : Instruction::SDiv; in getDecodedBinaryOpcode()
813 return IsFP ? -1 : Instruction::URem; in getDecodedBinaryOpcode()
815 return IsFP ? Instruction::FRem : Instruction::SRem; in getDecodedBinaryOpcode()
817 return IsFP ? -1 : Instruction::Shl; in getDecodedBinaryOpcode()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/AsmParser/ |
| D | LLParser.h | 579 bool IsFP);
581 bool IsFP);
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| /external/llvm-project/llvm/lib/AsmParser/ |
| D | LLParser.h | 577 bool IsFP);
579 unsigned Opc, bool IsFP);
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 550 unsigned getBoolExtOp(bool IsVec, bool IsFP) const;
555 bool IsFP);
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| /external/capstone/arch/AArch64/ |
| D | AArch64Disassembler.c | 998 bool IsFP; in DecodeSignedLdStInstruction() local
1172 IsFP = fieldFromInstruction(insn, 26, 1) != 0; in DecodeSignedLdStInstruction()
1175 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) in DecodeSignedLdStInstruction()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 2232 static unsigned getVectorComparison(ISD::CondCode CC, bool IsFP) { in getVectorComparison() argument
2236 return IsFP ? SystemZISD::VFCMPE : SystemZISD::VICMPE; in getVectorComparison()
2240 return IsFP ? SystemZISD::VFCMPHE : static_cast<SystemZISD::NodeType>(0); in getVectorComparison()
2244 return IsFP ? SystemZISD::VFCMPH : SystemZISD::VICMPH; in getVectorComparison()
2247 return IsFP ? static_cast<SystemZISD::NodeType>(0) : SystemZISD::VICMPHL; in getVectorComparison()
2258 static unsigned getVectorComparisonOrInvert(ISD::CondCode CC, bool IsFP, in getVectorComparisonOrInvert() argument
2260 if (unsigned Opcode = getVectorComparison(CC, IsFP)) { in getVectorComparisonOrInvert()
2265 CC = ISD::getSetCCInverse(CC, !IsFP); in getVectorComparisonOrInvert()
2266 if (unsigned Opcode = getVectorComparison(CC, IsFP)) { in getVectorComparisonOrInvert()
2306 bool IsFP = CmpOp0.getValueType().isFloatingPoint(); in lowerVectorSETCC() local
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstructionSelector.cpp | 862 bool IsFP = (RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI)->getID() != in selectSelectOpc() local
866 return IsFP ? AArch64::FCSELSrrr : AArch64::CSELWr; in selectSelectOpc()
868 return IsFP ? AArch64::FCSELDrrr : AArch64::CSELXr; in selectSelectOpc()
3713 bool IsFP = ScalarRB->getID() == AArch64::FPRRegBankID; in tryOptVectorDup() local
3715 if (IsFP) { in tryOptVectorDup()
3749 if (IsFP) { in tryOptVectorDup()
3757 if (IsFP) in tryOptVectorDup()
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| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 1072 bool IsFP = fieldFromInstruction(insn, 26, 1); in DecodeSignedLdStInstruction() local
1075 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) in DecodeSignedLdStInstruction()
|