| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.h | 176 bool IsInc) const;
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| D | AMDGPULegalizerInfo.cpp | 3819 bool IsInc) const { in legalizeAtomicIncDec()
3820 unsigned Opc = IsInc ? AMDGPU::G_AMDGPU_ATOMIC_INC : in legalizeAtomicIncDec()
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| /external/clang/lib/CodeGen/ |
| D | CGExprScalar.cpp | 354 bool IsInc);
1596 llvm::Value *InVal, bool IsInc) { in createBinOpInfoFromIncDec() argument
1601 BinOp.Opcode = IsInc ? BO_Add : BO_Sub; in createBinOpInfoFromIncDec()
1608 const UnaryOperator *E, llvm::Value *InVal, bool IsInc) { in EmitIncDecConsiderOverflowBehavior() argument
1610 llvm::ConstantInt::get(InVal->getType(), IsInc ? 1 : -1, true); in EmitIncDecConsiderOverflowBehavior()
1611 StringRef Name = IsInc ? "inc" : "dec"; in EmitIncDecConsiderOverflowBehavior()
1620 return EmitOverflowCheckedBinOp(createBinOpInfoFromIncDec(E, InVal, IsInc)); in EmitIncDecConsiderOverflowBehavior()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 562 ISD::MemIndexedMode &AM, bool &IsInc,
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| D | AArch64ISelLowering.cpp | 9987 bool &IsInc, in getIndexedAddressParts() argument
9999 IsInc = (Op->getOpcode() == ISD::ADD); in getIndexedAddressParts()
10021 bool IsInc; in getPreIndexedAddressParts() local
10022 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG)) in getPreIndexedAddressParts()
10024 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC; in getPreIndexedAddressParts()
10042 bool IsInc; in getPostIndexedAddressParts() local
10043 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG)) in getPostIndexedAddressParts()
10049 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC; in getPostIndexedAddressParts()
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| /external/llvm-project/clang/lib/CodeGen/ |
| D | CGExprScalar.cpp | 599 bool IsInc);
2315 llvm::Value *InVal, bool IsInc, in createBinOpInfoFromIncDec() argument
2321 BinOp.Opcode = IsInc ? BO_Add : BO_Sub; in createBinOpInfoFromIncDec()
2328 const UnaryOperator *E, llvm::Value *InVal, bool IsInc) { in EmitIncDecConsiderOverflowBehavior() argument
2330 llvm::ConstantInt::get(InVal->getType(), IsInc ? 1 : -1, true); in EmitIncDecConsiderOverflowBehavior()
2331 StringRef Name = IsInc ? "inc" : "dec"; in EmitIncDecConsiderOverflowBehavior()
2343 E, InVal, IsInc, E->getFPFeaturesInEffect(CGF.getLangOpts()))); in EmitIncDecConsiderOverflowBehavior()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAGHVX.cpp | 1914 bool IsInc = I == E-1 || SwapElems[I] < SwapElems[I+1]; in perfect() local
1917 while (++I < E-1 && IsInc == (SwapElems[I] < SwapElems[I+1])) in perfect()
1928 Res.Opc = IsInc ? Hexagon::V6_vshuffvdd : Hexagon::V6_vdealvdd; in perfect()
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAGHVX.cpp | 1953 bool IsInc = I == E-1 || SwapElems[I] < SwapElems[I+1]; in perfect() local
1956 while (++I < E-1 && IsInc == (SwapElems[I] < SwapElems[I+1])) in perfect()
1967 Res.Opc = IsInc ? Hexagon::V6_vshuffvdd : Hexagon::V6_vdealvdd; in perfect()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 803 ISD::MemIndexedMode &AM, bool &IsInc,
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| D | AArch64ISelLowering.cpp | 12729 bool &IsInc, in getIndexedAddressParts() argument
12743 IsInc = (Op->getOpcode() == ISD::ADD); in getIndexedAddressParts()
12765 bool IsInc; in getPreIndexedAddressParts() local
12766 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG)) in getPreIndexedAddressParts()
12768 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC; in getPreIndexedAddressParts()
12786 bool IsInc; in getPostIndexedAddressParts() local
12787 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG)) in getPostIndexedAddressParts()
12793 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC; in getPostIndexedAddressParts()
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 989 ISD::MemIndexedMode &AM, bool &IsInc,
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| D | AArch64ISelLowering.cpp | 15597 bool &IsInc, in getIndexedAddressParts() argument
15611 IsInc = (Op->getOpcode() == ISD::ADD); in getIndexedAddressParts()
15633 bool IsInc; in getPreIndexedAddressParts() local
15634 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG)) in getPreIndexedAddressParts()
15636 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC; in getPreIndexedAddressParts()
15654 bool IsInc; in getPostIndexedAddressParts() local
15655 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG)) in getPostIndexedAddressParts()
15661 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC; in getPostIndexedAddressParts()
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| /external/swiftshader/third_party/subzero/unittest/AssemblerX8632/ |
| D | GPRArith.cpp | 1360 const bool IsInc = std::string(#Inst).find("incl") != std::string::npos; \ in TEST_F()
1370 ASSERT_EQ(static_cast<uint32_t>(Value0 + (IsInc ? 1 : -1)), \ in TEST_F()
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| /external/swiftshader/third_party/subzero/unittest/AssemblerX8664/ |
| D | GPRArith.cpp | 1349 const bool IsInc = std::string(#Inst).find("incl") != std::string::npos; \ in TEST_F()
1359 ASSERT_EQ(static_cast<uint32_t>(Value0 + (IsInc ? 1 : -1)), \ in TEST_F()
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| /external/clang/lib/Sema/ |
| D | SemaExpr.cpp | 10173 bool IsInc, bool IsPrefix) { in CheckIncrementDecrementOperand() argument
10188 if (!IsInc) { in CheckIncrementDecrementOperand()
10198 S.Diag(OpLoc, diag::err_increment_decrement_enum) << IsInc << ResType; in CheckIncrementDecrementOperand()
10220 IsInc, IsPrefix); in CheckIncrementDecrementOperand()
10232 << ResType << int(IsInc) << Op->getSourceRange(); in CheckIncrementDecrementOperand()
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| /external/llvm-project/clang/lib/Sema/ |
| D | SemaExpr.cpp | 13126 bool IsInc, bool IsPrefix) { in CheckIncrementDecrementOperand() argument
13141 if (!IsInc) { in CheckIncrementDecrementOperand()
13151 S.Diag(OpLoc, diag::err_increment_decrement_enum) << IsInc << ResType; in CheckIncrementDecrementOperand()
13173 IsInc, IsPrefix); in CheckIncrementDecrementOperand()
13185 << ResType << int(IsInc) << Op->getSourceRange(); in CheckIncrementDecrementOperand()
13196 << IsInc << ResType; in CheckIncrementDecrementOperand()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 21268 static SDValue incDecVectorConstant(SDValue V, SelectionDAG &DAG, bool IsInc) { in incDecVectorConstant() argument
21285 if ((IsInc && EltC.isMaxValue()) || (!IsInc && EltC.isNullValue())) in incDecVectorConstant()
21288 NewVecC.push_back(DAG.getConstant(EltC + (IsInc ? 1 : -1), DL, EltVT)); in incDecVectorConstant()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 22496 static SDValue incDecVectorConstant(SDValue V, SelectionDAG &DAG, bool IsInc) { in incDecVectorConstant() argument
22513 if ((IsInc && EltC.isMaxValue()) || (!IsInc && EltC.isNullValue())) in incDecVectorConstant()
22516 NewVecC.push_back(DAG.getConstant(EltC + (IsInc ? 1 : -1), DL, EltVT)); in incDecVectorConstant()
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