Searched refs:IsLaneSizeD (Results 1 – 4 of 4) sorted by relevance
| /external/vixl/src/aarch64/ |
| D | assembler-sve-aarch64.cc | 134 VIXL_ASSERT(zd.IsLaneSizeD()); in and_()
143 VIXL_ASSERT(zd.IsLaneSizeD()); in bic()
152 VIXL_ASSERT(zd.IsLaneSizeD()); in eor()
161 VIXL_ASSERT(zd.IsLaneSizeD()); in orr()
2438 VIXL_ASSERT(zd.IsLaneSizeS() || zd.IsLaneSizeD()); in sdiv()
2455 VIXL_ASSERT(zd.IsLaneSizeS() || zd.IsLaneSizeD()); in sdivr()
2568 VIXL_ASSERT(zd.IsLaneSizeS() || zd.IsLaneSizeD()); in udiv()
2585 VIXL_ASSERT(zd.IsLaneSizeS() || zd.IsLaneSizeD()); in udivr()
2957 VIXL_ASSERT(zm.IsLaneSizeD()); in cmpeq()
2974 VIXL_ASSERT(zm.IsLaneSizeD()); in cmpge()
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| D | operands-aarch64.h | 597 (regoffset_.IsLaneSizeS() || regoffset_.IsLaneSizeD()) && !IsMulVl(); in IsScalarPlusVector()
602 (base_.IsLaneSizeS() || base_.IsLaneSizeD()) && in IsVectorPlusImmediate()
609 (base_.IsLaneSizeS() || base_.IsLaneSizeD()); in IsVectorPlusVector()
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| D | registers-aarch64.h | 170 bool IsLaneSizeD() const { return lane_size_ == kEncodedDRegSize; } in IsLaneSizeD() function
334 bool Is2D() const { return IsQ() && IsLaneSizeD(); } in Is2D()
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| D | assembler-aarch64.cc | 3639 V(shadd, NEON_SHADD, vd.IsVector() && !vd.IsLaneSizeD()) \
3640 V(uhadd, NEON_UHADD, vd.IsVector() && !vd.IsLaneSizeD()) \
3641 V(srhadd, NEON_SRHADD, vd.IsVector() && !vd.IsLaneSizeD()) \
3642 V(urhadd, NEON_URHADD, vd.IsVector() && !vd.IsLaneSizeD()) \
3643 V(shsub, NEON_SHSUB, vd.IsVector() && !vd.IsLaneSizeD()) \
3644 V(uhsub, NEON_UHSUB, vd.IsVector() && !vd.IsLaneSizeD()) \
3645 V(smax, NEON_SMAX, vd.IsVector() && !vd.IsLaneSizeD()) \
3646 V(smaxp, NEON_SMAXP, vd.IsVector() && !vd.IsLaneSizeD()) \
3647 V(smin, NEON_SMIN, vd.IsVector() && !vd.IsLaneSizeD()) \
3648 V(sminp, NEON_SMINP, vd.IsVector() && !vd.IsLaneSizeD()) \
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